[PATCH] D149933: [RISCV] Add X1 as implicit def of cm.jalt.

[Craig Topper via Phabricator via llvm-commits]

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This instruction updates the RA register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149933

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZc.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -142,6 +142,7 @@
   let Inst{6-2} = index;
 }
 
+let Defs = [X1] in
 def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
                          "cm.jalt", "$index">{
   bits<8> index;


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