[PATCH] D149841: AMDGPU/SDAG: Improve {extract,insert}_subvector lowering for 16-bit vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:1440
+         (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) &&
+        Start != 1)
+      return Op;
----------------
nhaehnle wrote:
> Joe_Nash wrote:
> > foad wrote:
> > > `Start != 1` is redundant now.
> > I'm not sure the Start == NumElt case will ever be hit.
> > But it looks like that can be removed in a follow up patch anyway.
> > LGTM
> It's an extract, so `Start == NumElt` should mean that we're extracting the high half of the source vector. Unless I'm extremely confused right now.
I think this is one of those cases that theoretically exists but is really hard to observe since the combiner would always just fold it to the source operand 


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  https://reviews.llvm.org/D149841/new/

https://reviews.llvm.org/D149841