[PATCH] D149771: [RISCV] Use setcc to truncate results in widenVectorOpsToi8

[Luke Lau via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9e9bf1e3ed9e: [RISCV] Use setcc to truncate results in widenVectorOpsToi8 (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149771/new/

https://reviews.llvm.org/D149771

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll


Index: llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -17,15 +17,13 @@
 ; CHECK-NEXT:    vwaddu.vv v16, v8, v12
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v16, a0, v12
-; CHECK-NEXT:    vand.vi v8, v18, 1
-; CHECK-NEXT:    vmsne.vi v10, v8, 0
-; CHECK-NEXT:    vand.vi v8, v16, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmsne.vi v8, v18, 0
+; CHECK-NEXT:    vmsne.vi v0, v16, 0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    add a1, a0, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT:    vslideup.vx v0, v10, a0
+; CHECK-NEXT:    vslideup.vx v0, v8, a0
 ; CHECK-NEXT:    ret
 	   %res = call <vscale x 32 x i1> @llvm.experimental.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
 	   ret <vscale x 32 x i1> %res
Index: llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -18,10 +18,8 @@
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmerge.vim v12, v10, 1, v0
 ; CHECK-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
-; CHECK-NEXT:    vnsrl.wi v8, v12, 8
-; CHECK-NEXT:    vand.vi v10, v8, 1
+; CHECK-NEXT:    vnsrl.wi v10, v12, 8
 ; CHECK-NEXT:    vmsne.vi v8, v10, 0
 ; CHECK-NEXT:    ret
 %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7318,9 +7318,9 @@
   SDValue WideN = DAG.getNode(N.getOpcode(), DL, VTs, WideOps);
   SmallVector<SDValue, 4> TruncVals;
   for (unsigned I = 0; I < NumVals; I++) {
-    TruncVals.push_back(DAG.getNode(ISD::TRUNCATE, DL,
-                                    N->getSimpleValueType(I),
-                                    SDValue(WideN.getNode(), I)));
+    TruncVals.push_back(
+        DAG.getSetCC(DL, N->getSimpleValueType(I), WideN.getValue(I),
+                     DAG.getConstant(0, DL, WideVT), ISD::SETNE));
   }
 
   if (TruncVals.size() > 1)


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