[llvm] 3928589 - [DAG] computeKnownBits - remove old ashr TODO comment

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-05-04T10:26:30+01:00
New Revision: 3928589314573565b9d8e46ec05d168af301a783

URL: https://github.com/llvm/llvm-project/commit/3928589314573565b9d8e46ec05d168af301a783
DIFF: https://github.com/llvm/llvm-project/commit/3928589314573565b9d8e46ec05d168af301a783.diff

LOG: [DAG] computeKnownBits - remove old ashr TODO comment

KnownBits::ashr now uses the minimum shift amount to try and extend the sign bit

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a155b4042d8a8..faae1cfc0a346 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3381,7 +3381,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known = KnownBits::ashr(Known, Known2);
-    // TODO: Add minimum shift high known sign bits.
     break;
   case ISD::FSHL:
   case ISD::FSHR: