[PATCH] D149811: [RISCV][CodeGen] Support Zhinx and Zhinxmin

[QIHAN CAI via Phabricator via llvm-commits]

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This patch was split from D122918 <https://reviews.llvm.org/D122918>.

Co-Author: @liaolucy @sunshaoce


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149811

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/half-arith-strict.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert-strict.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/half-frem.ll
  llvm/test/CodeGen/RISCV/half-imm.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/half-isnan.ll
  llvm/test/CodeGen/RISCV/half-mem.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/half-round-conv.ll
  llvm/test/CodeGen/RISCV/half-select-fcmp.ll
  llvm/test/CodeGen/RISCV/half-select-icmp.ll
  llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
  llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
  llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
  llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
  llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
  llvm/test/CodeGen/RISCV/zfh-imm.ll
  llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
  llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
  llvm/test/CodeGen/RISCV/zfhmin-imm.ll