[PATCH] D149665: [RISCV][CodeGen] Support Zdinx on RV64 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

LGTM with the RV32 specific pattern moved to the other patch.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:236
+let usesCustomInserter = 1 in {
+def PseudoQuietFLE_D_IN32X : PseudoQuietFCMP<FPR64IN32X>;
+def PseudoQuietFLT_D_IN32X : PseudoQuietFCMP<FPR64IN32X>;
----------------
This should be in the RV32 patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149665/new/

https://reviews.llvm.org/D149665