[llvm] 1cef77d - [RISCV] Fix intrinsic name in comment for lowerInterleavedLoad/lowerInterleavedStore. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-03T09:47:53-07:00
New Revision: 1cef77de1204c9d3e94c1f331d95476fc1413047

URL: https://github.com/llvm/llvm-project/commit/1cef77de1204c9d3e94c1f331d95476fc1413047
DIFF: https://github.com/llvm/llvm-project/commit/1cef77de1204c9d3e94c1f331d95476fc1413047.diff

LOG: [RISCV] Fix intrinsic name in comment for lowerInterleavedLoad/lowerInterleavedStore. NFC

Differential Revision: https://reviews.llvm.org/D149714

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3297fb1e417e..4eae05fa6e4d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15924,7 +15924,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
 ///
 /// Into:
-/// %ld2 = { <4 x i32>, <4 x i32> } call llvm.riscv.vlseg.v4i32.p0.i64(
+/// %ld2 = { <4 x i32>, <4 x i32> } call llvm.riscv.seg2.load.v4i32.p0.i64(
 ///                                        %ptr, i64 4)
 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
@@ -15973,8 +15973,8 @@ bool RISCVTargetLowering::lowerInterleavedLoad(
 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
-/// call void llvm.riscv.vsseg3.v4i32.p0.i64(%sub.v0, %sub.v1, %sub.v2,
-///                                          %ptr, i32 4)
+/// call void llvm.riscv.seg3.store.v4i32.p0.i64(%sub.v0, %sub.v1, %sub.v2,
+///                                              %ptr, i32 4)
 ///
 /// Note that the new shufflevectors will be removed and we'll only generate one
 /// vsseg3 instruction in CodeGen.