[llvm] 15723e6 - [AArch64] Additional tests for rshrn patterns. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2023-05-03T13:15:27+01:00
New Revision: 15723e6f8c2745639acfed6487bae577be5b37d7

URL: https://github.com/llvm/llvm-project/commit/15723e6f8c2745639acfed6487bae577be5b37d7
DIFF: https://github.com/llvm/llvm-project/commit/15723e6f8c2745639acfed6487bae577be5b37d7.diff

LOG: [AArch64] Additional tests for rshrn patterns. NFC

See D149636

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/neon-rshrn.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/neon-rshrn.ll b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
index 53880502c9ee1..7271050ada752 100644
--- a/llvm/test/CodeGen/AArch64/neon-rshrn.ll
+++ b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
@@ -769,7 +769,7 @@ entry:
 define <4 x i32> @rshrn_v4i64_33(<4 x i64> %a) {
 ; CHECK-LABEL: rshrn_v4i64_33:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov x8, #4294967296
+; CHECK-NEXT:    mov x8, #4294967296 // =0x100000000
 ; CHECK-NEXT:    dup v2.2d, x8
 ; CHECK-NEXT:    add v0.2d, v0.2d, v2.2d
 ; CHECK-NEXT:    add v1.2d, v1.2d, v2.2d
@@ -783,3 +783,137 @@ entry:
   %m = trunc <4 x i64> %s to <4 x i32>
   ret <4 x i32> %m
 }
+
+define <8 x i8> @rshrn_v8i16_5(<8 x i16> %a) {
+; CHECK-LABEL: rshrn_v8i16_5:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rshrn v0.8b, v0.8h, #5
+; CHECK-NEXT:    ret
+entry:
+  %b = add <8 x i16> %a, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  %s = lshr <8 x i16> %b, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  %m = trunc <8 x i16> %s to <8 x i8>
+  ret <8 x i8> %m
+}
+
+define <4 x i16> @rshrn_v4i32_4(<4 x i32> %a) {
+; CHECK-LABEL: rshrn_v4i32_4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rshrn v0.4h, v0.4s, #4
+; CHECK-NEXT:    ret
+entry:
+  %b = add <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
+  %s = lshr <4 x i32> %b, <i32 4, i32 4, i32 4, i32 4>
+  %m = trunc <4 x i32> %s to <4 x i16>
+  ret <4 x i16> %m
+}
+
+define <2 x i32> @rshrn_v2i64_5(<2 x i64> %a) {
+; CHECK-LABEL: rshrn_v2i64_5:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rshrn v0.2s, v0.2d, #5
+; CHECK-NEXT:    ret
+entry:
+  %b = add <2 x i64> %a, <i64 16, i64 16>
+  %s = lshr <2 x i64> %b, <i64 5, i64 5>
+  %m = trunc <2 x i64> %s to <2 x i32>
+  ret <2 x i32> %m
+}
+
+define void @rshrn_v8i32i8_5(<8 x i32> %a, ptr %p) {
+; CHECK-LABEL: rshrn_v8i32i8_5:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v2.4h, #16
+; CHECK-NEXT:    xtn v1.4h, v1.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    add v1.4h, v1.4h, v2.4h
+; CHECK-NEXT:    add v0.4h, v0.4h, v2.4h
+; CHECK-NEXT:    ushr v1.4h, v1.4h, #5
+; CHECK-NEXT:    ushr v0.4h, v0.4h, #5
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    str d0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %b = add <8 x i32> %a, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  %s = lshr <8 x i32> %b, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  %m = trunc <8 x i32> %s to <8 x i8>
+  store <8 x i8> %m, ptr %p
+  ret void
+}
+
+define void @rshrn_v4i64i16_4(<4 x i64> %a, ptr %p) {
+; CHECK-LABEL: rshrn_v4i64i16_4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v2.2s, #8
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    add v1.2s, v1.2s, v2.2s
+; CHECK-NEXT:    add v0.2s, v0.2s, v2.2s
+; CHECK-NEXT:    ushr v1.2s, v1.2s, #4
+; CHECK-NEXT:    ushr v0.2s, v0.2s, #4
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    str d0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %b = add <4 x i64> %a, <i64 8, i64 8, i64 8, i64 8>
+  %s = lshr <4 x i64> %b, <i64 4, i64 4, i64 4, i64 4>
+  %m = trunc <4 x i64> %s to <4 x i16>
+  store <4 x i16> %m, ptr %p
+  ret void
+}
+
+define void @rshrn_v4i16_5(<4 x i16> %a, ptr %p) {
+; CHECK-LABEL: rshrn_v4i16_5:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v1.4h, #16
+; CHECK-NEXT:    add v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ushr v0.4h, v0.4h, #5
+; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %b = add <4 x i16> %a, <i16 16, i16 16, i16 16, i16 16>
+  %s = lshr <4 x i16> %b, <i16 5, i16 5, i16 5, i16 5>
+  %m = trunc <4 x i16> %s to <4 x i8>
+  store <4 x i8> %m, ptr %p
+  ret void
+}
+
+define void @rshrn_v2i32_4(<2 x i32> %a, ptr %p) {
+; CHECK-LABEL: rshrn_v2i32_4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v1.2s, #8
+; CHECK-NEXT:    add v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    ushr v0.2s, v0.2s, #4
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    strh w9, [x0]
+; CHECK-NEXT:    strh w8, [x0, #2]
+; CHECK-NEXT:    ret
+entry:
+  %b = add <2 x i32> %a, <i32 8, i32 8>
+  %s = lshr <2 x i32> %b, <i32 4, i32 4>
+  %m = trunc <2 x i32> %s to <2 x i16>
+  store <2 x i16> %m, ptr %p
+  ret void
+}
+
+define void @rshrn_v1i64_5(<1 x i64> %a, ptr %p) {
+; CHECK-LABEL: rshrn_v1i64_5:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov w8, #16 // =0x10
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    add d0, d0, d1
+; CHECK-NEXT:    ushr d0, d0, #5
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %b = add <1 x i64> %a, <i64 16>
+  %s = lshr <1 x i64> %b, <i64 5>
+  %m = trunc <1 x i64> %s to <1 x i32>
+  store <1 x i32> %m, ptr %p
+  ret void
+}