[PATCH] D149711: [PowerPC] Remove asserts from the disassembler.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai, amyk.
Herald added subscribers: shchenz, kbarton, hiraditya.
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My previous patch had added a couple of asserts to the disassembler.
The problem with this is that the disassembler is not just used for the
text section it is also used to disassemble the data section of an
object where the bytes do not necessarily represent instructions. If the
data in the data section happens to look like an illegal instruction
then llvm-objdump will assert on data because it is finding an illegal
instruction that is not actually an instruction at all.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149711

Files:
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt


Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -23,3 +23,12 @@
 
 # CHECK: dsubq. 2, 6, 4
 0xfc 0x46 0x24 0x05
+
+# This is actually the encoding for an invalid instruction.
+# However, we check it here because the disassembler shouldn't check if an
+# instruction is valid when decoding it because llvm-objdump uses the decoder
+# for data sections as well as text sections and we do not want to assert in
+# cases where we are decoding a data section that happens to match an invalid
+# instruction.
+# CHECK: dsubq 0, 6, 30
+0xfc 0x06 0xfc 0x04
Index: llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
===================================================================
--- llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -115,8 +115,6 @@
 static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
-  assert(RegNo <= 30 && "Expecting a register number no more than 30.");
-  assert((RegNo & 1) == 0 && "Expecting an even register number.");
   return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
 }
 


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