[llvm] cdeb4a0 - [gn] port 243e8f8d23ac71 (llvm-min-tblgen)
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Tue May 2 17:04:42 PDT 2023
Author: Nico Weber
Date: 2023-05-02T20:04:32-04:00
New Revision: cdeb4a0aac0e8b3f7414bff9f6052267515fe63c
URL: https://github.com/llvm/llvm-project/commit/cdeb4a0aac0e8b3f7414bff9f6052267515fe63c
DIFF: https://github.com/llvm/llvm-project/commit/cdeb4a0aac0e8b3f7414bff9f6052267515fe63c.diff
LOG: [gn] port 243e8f8d23ac71 (llvm-min-tblgen)
Added:
Modified:
llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn
llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn
llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Removed:
################################################################################
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn
index c6d80b2be3f6b..6ce92c9149f0f 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn
@@ -4,6 +4,7 @@ tablegen("ACC") {
visibility = [ ":acc_gen" ]
args = [ "-gen-directive-decl" ]
output_name = "ACC.h.inc"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
tablegen("ACCcpp") {
@@ -11,6 +12,7 @@ tablegen("ACCcpp") {
args = [ "-gen-directive-impl" ]
output_name = "ACC.inc"
td_file = "ACC.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
group("acc_gen") {
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn
index d99b8b5a1e27d..739f3383c1740 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn
@@ -5,11 +5,13 @@ tablegen("OMPh") {
args = [ "-gen-directive-decl" ]
output_name = "OMP.h.inc"
td_file = "OMP.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
tablegen("OMP") {
visibility = [ ":public_tablegen" ]
args = [ "-gen-directive-impl" ]
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
# Groups all tablegen() calls that create .inc files that are included in
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
index 148fe951b432e..a594d2afbf7d6 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
@@ -3,18 +3,21 @@ import("//llvm/utils/TableGen/tablegen.gni")
tablegen("Attributes") {
visibility = [ ":public_tablegen" ]
args = [ "-gen-attrs" ]
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
tablegen("IntrinsicImpl") {
visibility = [ "//llvm/lib/IR" ]
args = [ "-gen-intrinsic-impl" ]
td_file = "Intrinsics.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
tablegen("IntrinsicEnums") {
visibility = [ ":public_tablegen" ]
args = [ "-gen-intrinsic-enums" ]
td_file = "Intrinsics.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
template("gen_arch_intrinsics") {
@@ -26,6 +29,7 @@ template("gen_arch_intrinsics") {
"-intrinsic-prefix=${invoker.intrinsic_prefix}",
]
td_file = "Intrinsics.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
}
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
index 0644daaa9daa7..aecb65ab6c728 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
@@ -4,6 +4,7 @@ tablegen("RISCVTargetParserDef") {
visibility = [ ":gen" ]
args = [ "-gen-riscv-target-def" ]
td_file = "//llvm/lib/Target/RISCV/RISCV.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
group("gen") {
diff --git a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
index 4f1bab7957d27..122baedfa292c 100644
--- a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
@@ -5,6 +5,7 @@ tablegen("GenVT") {
visibility = [ ":SupportTests" ]
args = [ "-gen-vt" ]
td_file = "//llvm/include/llvm/CodeGen/ValueTypes.td"
+ tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
}
unittest("SupportTests") {
diff --git a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
index 1f201bd783b73..4fe24b0e0cb51 100644
--- a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
@@ -1,5 +1,28 @@
+source_set("llvm-min-tblgen-sources") {
+ sources = [
+ "Attributes.cpp",
+ "CodeGenIntrinsics.cpp",
+ "DirectiveEmitter.cpp",
+ "IntrinsicEmitter.cpp",
+ "RISCVTargetDefEmitter.cpp",
+ "SDNodeProperties.cpp",
+ "TableGen.cpp",
+ "VTEmitter.cpp",
+ ]
+}
+
+executable("llvm-min-tblgen") {
+ deps = [
+ ":llvm-min-tblgen-sources",
+ "//llvm/include/llvm/Config:llvm-config",
+ "//llvm/lib/Support",
+ "//llvm/lib/TableGen",
+ ]
+}
+
executable("llvm-tblgen") {
deps = [
+ ":llvm-min-tblgen-sources",
"//llvm/include/llvm/Config:llvm-config",
"//llvm/lib/Support",
"//llvm/lib/TableGen",
@@ -9,7 +32,6 @@ executable("llvm-tblgen") {
"AsmMatcherEmitter.cpp",
"AsmWriterEmitter.cpp",
"AsmWriterInst.cpp",
- "Attributes.cpp",
"CTagsEmitter.cpp",
"CallingConvEmitter.cpp",
"CodeEmitterGen.cpp",
@@ -17,7 +39,6 @@ executable("llvm-tblgen") {
"CodeGenHwModes.cpp",
"CodeGenInstAlias.cpp",
"CodeGenInstruction.cpp",
- "CodeGenIntrinsics.cpp",
"CodeGenMapTable.cpp",
"CodeGenRegisters.cpp",
"CodeGenSchedule.cpp",
@@ -32,7 +53,6 @@ executable("llvm-tblgen") {
"DFAPacketizerEmitter.cpp",
"DXILEmitter.cpp",
"DecoderEmitter.cpp",
- "DirectiveEmitter.cpp",
"DisassemblerEmitter.cpp",
"ExegesisEmitter.cpp",
"FastISelEmitter.cpp",
@@ -41,22 +61,17 @@ executable("llvm-tblgen") {
"InfoByHwMode.cpp",
"InstrDocsEmitter.cpp",
"InstrInfoEmitter.cpp",
- "IntrinsicEmitter.cpp",
"OptEmitter.cpp",
"OptParserEmitter.cpp",
"OptRSTEmitter.cpp",
"PredicateExpander.cpp",
"PseudoLoweringEmitter.cpp",
- "RISCVTargetDefEmitter.cpp",
"RegisterBankEmitter.cpp",
"RegisterInfoEmitter.cpp",
- "SDNodeProperties.cpp",
"SearchableTableEmitter.cpp",
"SubtargetEmitter.cpp",
"SubtargetFeatureInfo.cpp",
- "TableGen.cpp",
"Types.cpp",
- "VTEmitter.cpp",
"VarLenCodeEmitterGen.cpp",
"WebAssemblyDisassemblerEmitter.cpp",
"X86DisassemblerTables.cpp",
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