[PATCH] D149665: [RISCV][CodeGen] Support Zdinx on RV64 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/docs/RISCVUsage.rst:104
+     ``Zdinx RV32``   Assembly Support
+     ``Zdinx RV64``   Supported
      ``Zfh``          Supported
----------------
Can we keep this on one line and write something like

`Assembly Support for RV32. Full support for RV64.`


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:893
       assert((Subtarget->is64Bit() || APF.isZero()) && "Unexpected constant");
-      Opc = Subtarget->is64Bit() ? RISCV::FMV_D_X : RISCV::FCVT_D_W;
+      bool IsZdinx = Subtarget->hasStdExtZdinx();
+      if (Subtarget->is64Bit())
----------------
Is -> Has


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149665/new/

https://reviews.llvm.org/D149665