[llvm] 16980c0 - [AMDGPU] Make use of new tablegen operator !range. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-05-02T10:36:15+01:00
New Revision: 16980c08cb0c519c78d8f11821d783791450b62f

URL: https://github.com/llvm/llvm-project/commit/16980c08cb0c519c78d8f11821d783791450b62f
DIFF: https://github.com/llvm/llvm-project/commit/16980c08cb0c519c78d8f11821d783791450b62f.diff

LOG: [AMDGPU] Make use of new tablegen operator !range. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MIMGInstructions.td
    llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 57afcbc255f63..0420cf0474832 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -241,14 +241,10 @@ class NSAHelper {
   int NSA;
 }
 
-// This class used to use !foldl to memoize the AddrAsmNames list.
-// It turned out that that was much slower than using !filter.
 class MIMGNSAHelper<int num_addrs,
                     list<RegisterClass> addr_types=!listsplat(VGPR_32, num_addrs)>
   : NSAHelper<> {
-  list<string> AddrAsmNames =
-    !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11],
-                        !lt(i, num_addrs)), "vaddr" # i);
+  list<string> AddrAsmNames = !foreach(i, !range(num_addrs), "vaddr" # i);
   let AddrIns = !dag(ins, addr_types, AddrAsmNames);
   let AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]";
 
@@ -267,9 +263,7 @@ class PartialNSAHelper<int num_addrs, int max_addr, RegisterClass LastAddrRC>
       !listsplat(VGPR_32, num_addrs));
 
   int VAddrCount = !if(!gt(num_addrs, max_addr), max_addr, num_addrs);
-  list<string> AddrAsmNames =
-    !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11],
-             !lt(i, VAddrCount)), "vaddr" # i);
+  list<string> AddrAsmNames =  !foreach(i, !range(VAddrCount), "vaddr" # i);
 
   let AddrIns = !dag(ins, addr_types, AddrAsmNames);
   let AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]";

diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 5b8aac40b95b3..5c2e88727296c 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -10,16 +10,6 @@
 //  Subregister declarations
 //===----------------------------------------------------------------------===//
 
-class Indexes<int N> {
-  list<int> all = [0,   1,  2,  3,  4,  5,  6 , 7,
-                   8,   9, 10, 11, 12, 13, 14, 15,
-                   16, 17, 18, 19, 20, 21, 22, 23,
-                   24, 25, 26, 27, 28, 29, 30, 31];
-
-  // Returns list of indexes [0..N)
-  list<int> slice = !filter(i, all, !lt(i, N));
-}
-
 let Namespace = "AMDGPU" in {
 
 def lo16 : SubRegIndex<16, 0>;
@@ -35,13 +25,11 @@ foreach Index = 1...31 in {
 }
 
 foreach Size = {2...6,8,16} in {
-  foreach Index = Indexes<!sub(33, Size)>.slice in {
-    def !interleave(!foreach(cur, Indexes<Size>.slice, "sub"#!add(cur, Index)),
-                    "_") :
+  foreach Index = !range(!sub(33, Size)) in {
+    def !interleave(!foreach(cur, !range(Size), "sub"#!add(cur, Index)), "_") :
       SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
       let CoveringSubRegIndices =
-        !foreach(cur, Indexes<Size>.slice,
-                 !cast<SubRegIndex>(sub#!add(cur, Index)));
+        !foreach(cur, !range(Size), !cast<SubRegIndex>(sub#!add(cur, Index)));
     }
   }
 }