[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

All CPU name additions should be mentioned in the RISC-V section of llvm/docs/ReleaseNotes.rst


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495