[llvm] 09f6bdd - [RISCV] Remove INVALID from the list of CPUs in RISCVTargetParser. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-01T15:26:09-07:00
New Revision: 09f6bdda24d57c40cd4bd27c598d875c226cd5f2

URL: https://github.com/llvm/llvm-project/commit/09f6bdda24d57c40cd4bd27c598d875c226cd5f2
DIFF: https://github.com/llvm/llvm-project/commit/09f6bdda24d57c40cd4bd27c598d875c226cd5f2.diff

LOG: [RISCV] Remove INVALID from the list of CPUs in RISCVTargetParser. NFC

This value is never used outside and is only used as a sentinel
internally which we can solve with other means.

Added: 
    

Modified: 
    llvm/lib/TargetParser/RISCVTargetParser.cpp
    llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 6a357542ef08b..22b52357c1978 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -29,7 +29,6 @@ struct CPUInfo {
   StringLiteral Name;
   CPUKind Kind;
   StringLiteral DefaultMarch;
-  bool isInvalid() const { return DefaultMarch.empty(); }
   bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
 };
 
@@ -55,12 +54,13 @@ bool parseCPU(StringRef CPU, bool IsRV64) {
 }
 
 bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
-  CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
-  #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
+  std::optional<CPUKind> Kind =
+      llvm::StringSwitch<std::optional<CPUKind>>(TuneCPU)
+#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
   #include "llvm/TargetParser/RISCVTargetParserDef.inc"
-      .Default(CK_INVALID);
+      .Default(std::nullopt);
 
-  if (Kind != CK_INVALID)
+  if (Kind.has_value())
     return true;
 
   // Fallback to parsing as a CPU.
@@ -76,14 +76,14 @@ StringRef getMArchFromMcpu(StringRef CPU) {
 
 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
   for (const auto &C : RISCVCPUInfo) {
-    if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
+    if (IsRV64 == C.is64Bit())
       Values.emplace_back(C.Name);
   }
 }
 
 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
   for (const auto &C : RISCVCPUInfo) {
-    if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
+    if (IsRV64 == C.is64Bit())
       Values.emplace_back(C.Name);
   }
 #define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));

diff  --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 18e98ff9b9f9c..12174fd83f566 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -52,7 +52,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
      << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
      << "#endif\n\n";
 
-  OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
   // Iterate on all definition records.
   for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
     std::string MArch = Rec->getValueAsString("DefaultMarch").str();