[PATCH] D149486: [RISCV] Strengthen atomic ordering for sequentially consistent Loads

[Paul Kirth via Phabricator via llvm-commits]

paulkirth added a comment.

In D149486#4307064 <https://reviews.llvm.org/D149486#4307064>, @jrtc27 wrote:

>> avoid an ABI break in the future.
>
> There will always be an ABI break if a model conflicting with the existing de-facto standard that has been in use for multiple years is adopted. That makes me very nervous.

I'll update the summary with a more substantial explanation, closer to the overall sentiment from the psABI PR.

>From https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378#issue-1689133614

  We believe that the Table A.7 mapping, together with the new instructions it requires, will be necessary to be performance competitive with other architectures for seq_cst operations, especially for processor designs similar to current out-of-order mobile cores. Starting with the ABI described here will allow some platforms to completely avoid an ABI break when switching to A.7. Platforms that already have code compiled to (unmodified) A.6 will get more time to gradually replace that code in preparation for such a switch.


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https://reviews.llvm.org/D149486