[PATCH] D149488: [RISCV] Use AMOSWAP for 32 and 64-bit atomic stores

[Paul Kirth via Phabricator via llvm-commits]

paulkirth added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/atomic-load-store.ll:1128
+; RV32IA:       # %bb.0:
+; RV32IA-NEXT:    amoswap.w.rl a0, a1, (a0)
+; RV32IA-NEXT:    ret
----------------
jrtc27 wrote:
> Why are we writing a killed value to a0?
After Atomic Expand the store is rewritten from:
```
store atomic i32 %b, ptr %a seq_cst, align 4
```

to

```
%1 = atomicrmw xchg ptr %a, i32 %b release, align 4
```

The langref says the semantics for xchg here should be :`*ptr = val`,  so I think that's all correct. https://llvm.org/docs/LangRef.html#id229

>From there, the rest of the codegen is consistent w/ the contents of https://github.com/llvm/llvm-project/blob/f762798599171efca03964f4371cc8104d2392f9/llvm/test/CodeGen/RISCV/atomic-rmw.ll#L9844

If that is wrong, then I guess we need to adjust the tablegen for AMOSWAP?



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