[PATCH] D148624: [AArch64] Add sign bits handling for vector compare nodes

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 518457.
dmgreen retitled this revision from "[AArch64] Add sign bits for vector compare nodes" to "[AArch64] Add sign bits handling for vector compare nodes".
dmgreen edited the summary of this revision.
dmgreen added reviewers: samtebbs, jaykang10.
dmgreen added a comment.

Updated to also handle VASHR+VSHL sign_extend_inreg, similar to the generic DAG combine, which helps show this doing more.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148624/new/

https://reviews.llvm.org/D148624

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

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