[lld] 176cc70 - [NFC][LLD] Disambiguate RISCV and llvm::RISCV

[Vitaly Buka via llvm-commits]

Author: Vitaly Buka
Date: 2023-04-29T19:06:37-07:00
New Revision: 176cc70abe8d85df9aae223e0b35ce65238c4333

URL: https://github.com/llvm/llvm-project/commit/176cc70abe8d85df9aae223e0b35ce65238c4333
DIFF: https://github.com/llvm/llvm-project/commit/176cc70abe8d85df9aae223e0b35ce65238c4333.diff

LOG: [NFC][LLD] Disambiguate RISCV and llvm::RISCV

Build is broken after ee9cbe35.

Added: 
    

Modified: 
    lld/ELF/Arch/RISCV.cpp

Removed: 
    


################################################################################
diff  --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 26977015dab3a..0f233d4fbb97c 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -27,9 +27,9 @@ using namespace lld::elf;
 
 namespace {
 
-class RISCV final : public TargetInfo {
+class RISCVTargetInfo final : public TargetInfo {
 public:
-  RISCV();
+  RISCVTargetInfo();
   uint32_t calcEFlags() const override;
   int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void writeGotHeader(uint8_t *buf) const override;
@@ -101,7 +101,7 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
          (extractBits(imm, 4, 0) << 7);
 }
 
-RISCV::RISCV() {
+RISCVTargetInfo::RISCVTargetInfo() {
   copyRel = R_RISCV_COPY;
   pltRel = R_RISCV_JUMP_SLOT;
   relativeRel = R_RISCV_RELATIVE;
@@ -136,7 +136,7 @@ static uint32_t getEFlags(InputFile *f) {
   return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags;
 }
 
-uint32_t RISCV::calcEFlags() const {
+uint32_t RISCVTargetInfo::calcEFlags() const {
   // If there are only binary input files (from -b binary), use a
   // value of 0 for the ELF header flags.
   if (ctx.objectFiles.empty())
@@ -163,7 +163,8 @@ uint32_t RISCV::calcEFlags() const {
   return target;
 }
 
-int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
+int64_t RISCVTargetInfo::getImplicitAddend(const uint8_t *buf,
+                                           RelType type) const {
   switch (type) {
   default:
     internalLinkerError(getErrorLocation(buf),
@@ -189,21 +190,21 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
   }
 }
 
-void RISCV::writeGotHeader(uint8_t *buf) const {
+void RISCVTargetInfo::writeGotHeader(uint8_t *buf) const {
   if (config->is64)
     write64le(buf, mainPart->dynamic->getVA());
   else
     write32le(buf, mainPart->dynamic->getVA());
 }
 
-void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
+void RISCVTargetInfo::writeGotPlt(uint8_t *buf, const Symbol &s) const {
   if (config->is64)
     write64le(buf, in.plt->getVA());
   else
     write32le(buf, in.plt->getVA());
 }
 
-void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
+void RISCVTargetInfo::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
   if (config->writeAddends) {
     if (config->is64)
       write64le(buf, s.getVA());
@@ -212,7 +213,7 @@ void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
   }
 }
 
-void RISCV::writePltHeader(uint8_t *buf) const {
+void RISCVTargetInfo::writePltHeader(uint8_t *buf) const {
   // 1: auipc t2, %pcrel_hi(.got.plt)
   // sub t1, t1, t3
   // l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve
@@ -233,8 +234,8 @@ void RISCV::writePltHeader(uint8_t *buf) const {
   write32le(buf + 28, itype(JALR, 0, X_T3, 0));
 }
 
-void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
-                     uint64_t pltEntryAddr) const {
+void RISCVTargetInfo::writePlt(uint8_t *buf, const Symbol &sym,
+                               uint64_t pltEntryAddr) const {
   // 1: auipc t3, %pcrel_hi(f at .got.plt)
   // l[wd] t3, %pcrel_lo(1b)(t3)
   // jalr t1, t3
@@ -246,13 +247,13 @@ void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
   write32le(buf + 12, itype(ADDI, 0, 0, 0));
 }
 
-RelType RISCV::getDynRel(RelType type) const {
+RelType RISCVTargetInfo::getDynRel(RelType type) const {
   return type == target->symbolicRel ? type
                                      : static_cast<RelType>(R_RISCV_NONE);
 }
 
-RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
-                          const uint8_t *loc) const {
+RelExpr RISCVTargetInfo::getRelExpr(const RelType type, const Symbol &s,
+                                    const uint8_t *loc) const {
   switch (type) {
   case R_RISCV_NONE:
     return R_NONE;
@@ -313,7 +314,8 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
   }
 }
 
-void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
+void RISCVTargetInfo::relocate(uint8_t *loc, const Relocation &rel,
+                               uint64_t val) const {
   const unsigned bits = config->wordsize * 8;
 
   switch (rel.type) {
@@ -754,7 +756,7 @@ static bool relax(InputSection &sec) {
 // target at a higher fixed address, invalidating an earlier relaxation. Any
 // change in section sizes can have cascading effect and require another
 // relaxation pass.
-bool RISCV::relaxOnce(int pass) const {
+bool RISCVTargetInfo::relaxOnce(int pass) const {
   llvm::TimeTraceScope timeScope("RISC-V relaxOnce");
   if (config->relocatable)
     return false;
@@ -1073,6 +1075,6 @@ void elf::mergeRISCVAttributesSections() {
 }
 
 TargetInfo *elf::getRISCVTargetInfo() {
-  static RISCV target;
+  static RISCVTargetInfo target;
   return ⌖
 }