[llvm] e744e51 - [SelectionDAG] Rename ADDCARRY/SUBCARRY to UADDO_CARRY/USUBO_CARRY (NFC)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 29 12:00:29 PDT 2023
Author: Sergei Barannikov
Date: 2023-04-29T21:59:58+03:00
New Revision: e744e51b121dde1f2eaf30b63090a1a8f9e73085
URL: https://github.com/llvm/llvm-project/commit/e744e51b121dde1f2eaf30b63090a1a8f9e73085
DIFF: https://github.com/llvm/llvm-project/commit/e744e51b121dde1f2eaf30b63090a1a8f9e73085.diff
LOG: [SelectionDAG] Rename ADDCARRY/SUBCARRY to UADDO_CARRY/USUBO_CARRY (NFC)
This will make them consistent with other overflow-aware nodes.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D148196
Added:
Modified:
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
llvm/lib/Target/CSKY/CSKYISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.h
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 9120d97e3cfb4..b49066d3751c4 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -263,9 +263,9 @@ enum NodeType {
/// These nodes take two operands of the same value type, and produce two
/// results. The first result is the normal add or sub result, the second
/// result is the carry flag result.
- /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
+ /// FIXME: These nodes are deprecated in favor of UADDO_CARRY and USUBO_CARRY.
/// They are kept around for now to provide a smooth transition path
- /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
+ /// toward the use of UADDO_CARRY/USUBO_CARRY and will eventually be removed.
ADDC,
SUBC,
@@ -297,11 +297,11 @@ enum NodeType {
/// it, as the carry is a regular value rather than a glue, which allows
/// further optimisation.
///
- /// These opcodes are
diff erent from [US]{ADD,SUB}O in that ADDCARRY/SUBCARRY
- /// consume and produce a carry/borrow, whereas [US]{ADD,SUB}O produce an
- /// overflow.
- ADDCARRY,
- SUBCARRY,
+ /// These opcodes are
diff erent from [US]{ADD,SUB}O in that
+ /// U{ADD,SUB}O_CARRY consume and produce a carry/borrow, whereas
+ /// [US]{ADD,SUB}O produce an overflow.
+ UADDO_CARRY,
+ USUBO_CARRY,
/// Carry-using overflow-aware nodes for multiple precision addition and
/// subtraction. These nodes take three operands: The first two are normal lhs
@@ -752,7 +752,7 @@ enum NodeType {
/// op #2 is a boolean indicating if there is an incoming carry. This
/// operator checks the result of "LHS - RHS - Carry", and can be used to
/// compare two wide integers:
- /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
+ /// (setcccarry lhshi rhshi (usubo_carry lhslo rhslo) cc).
/// Only valid for integers.
SETCCCARRY,
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 842ecc751d12e..d8e8e18aca823 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -423,11 +423,12 @@ namespace {
SDValue visitSUBC(SDNode *N);
SDValue visitSUBO(SDNode *N);
SDValue visitADDE(SDNode *N);
- SDValue visitADDCARRY(SDNode *N);
+ SDValue visitUADDO_CARRY(SDNode *N);
SDValue visitSADDO_CARRY(SDNode *N);
- SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
+ SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
+ SDNode *N);
SDValue visitSUBE(SDNode *N);
- SDValue visitSUBCARRY(SDNode *N);
+ SDValue visitUSUBO_CARRY(SDNode *N);
SDValue visitSSUBO_CARRY(SDNode *N);
SDValue visitMUL(SDNode *N);
SDValue visitMULFIX(SDNode *N);
@@ -1876,10 +1877,10 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::SSUBO:
case ISD::USUBO: return visitSUBO(N);
case ISD::ADDE: return visitADDE(N);
- case ISD::ADDCARRY: return visitADDCARRY(N);
+ case ISD::UADDO_CARRY: return visitUADDO_CARRY(N);
case ISD::SADDO_CARRY: return visitSADDO_CARRY(N);
case ISD::SUBE: return visitSUBE(N);
- case ISD::SUBCARRY: return visitSUBCARRY(N);
+ case ISD::USUBO_CARRY: return visitUSUBO_CARRY(N);
case ISD::SSUBO_CARRY: return visitSSUBO_CARRY(N);
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
@@ -2976,7 +2977,7 @@ static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
if (V.getResNo() != 1)
return SDValue();
- if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
+ if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY &&
V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
return SDValue();
@@ -3098,16 +3099,16 @@ SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
}
}
- // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
- if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
+ // (add X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry)
+ if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) &&
N1.getResNo() == 0)
- return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
+ return DAG.getNode(ISD::UADDO_CARRY, DL, N1->getVTList(),
N0, N1.getOperand(0), N1.getOperand(2));
- // (add X, Carry) -> (addcarry X, 0, Carry)
- if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
+ // (add X, Carry) -> (uaddo_carry X, 0, Carry)
+ if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT))
if (SDValue Carry = getAsCarry(TLI, N1))
- return DAG.getNode(ISD::ADDCARRY, DL,
+ return DAG.getNode(ISD::UADDO_CARRY, DL,
DAG.getVTList(VT, Carry.getValueType()), N0,
DAG.getConstant(0, DL, VT), Carry);
@@ -3238,20 +3239,20 @@ SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
if (VT.isVector())
return SDValue();
- // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
+ // (uaddo X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry)
// If Y + 1 cannot overflow.
- if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
+ if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) {
SDValue Y = N1.getOperand(0);
SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
- return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
+ return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, Y,
N1.getOperand(2));
}
- // (uaddo X, Carry) -> (addcarry X, 0, Carry)
- if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
+ // (uaddo X, Carry) -> (uaddo_carry X, 0, Carry)
+ if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT))
if (SDValue Carry = getAsCarry(TLI, N1))
- return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
+ return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0,
DAG.getConstant(0, SDLoc(N), VT), Carry);
return SDValue();
@@ -3276,7 +3277,7 @@ SDValue DAGCombiner::visitADDE(SDNode *N) {
return SDValue();
}
-SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
+SDValue DAGCombiner::visitUADDO_CARRY(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);
@@ -3286,16 +3287,16 @@ SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (N0C && !N1C)
- return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
+ return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
- // fold (addcarry x, y, false) -> (uaddo x, y)
+ // fold (uaddo_carry x, y, false) -> (uaddo x, y)
if (isNullConstant(CarryIn)) {
if (!LegalOperations ||
TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
}
- // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
+ // fold (uaddo_carry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
if (isNullConstant(N0) && isNullConstant(N1)) {
EVT VT = N0.getValueType();
EVT CarryVT = CarryIn.getValueType();
@@ -3306,20 +3307,20 @@ SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
DAG.getConstant(0, DL, CarryVT));
}
- if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
+ if (SDValue Combined = visitUADDO_CARRYLike(N0, N1, CarryIn, N))
return Combined;
- if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
+ if (SDValue Combined = visitUADDO_CARRYLike(N1, N0, CarryIn, N))
return Combined;
// We want to avoid useless duplication.
- // TODO: This is done automatically for binary operations. As ADDCARRY is
+ // TODO: This is done automatically for binary operations. As UADDO_CARRY is
// not a binary operation, this is not really possible to leverage this
// existing mechanism for it. However, if more operations require the same
// deduplication logic, then it may be worth generalize.
SDValue Ops[] = {N1, N0, CarryIn};
SDNode *CSENode =
- DAG.getNodeIfExists(ISD::ADDCARRY, N->getVTList(), Ops, N->getFlags());
+ DAG.getNodeIfExists(ISD::UADDO_CARRY, N->getVTList(), Ops, N->getFlags());
if (CSENode)
return SDValue(CSENode, 0);
@@ -3351,28 +3352,29 @@ SDValue DAGCombiner::visitSADDO_CARRY(SDNode *N) {
/**
* If we are facing some sort of diamond carry propapagtion pattern try to
* break it up to generate something like:
- * (addcarry X, 0, (addcarry A, B, Z):Carry)
+ * (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)
*
* The end result is usually an increase in operation required, but because the
* carry is now linearized, other transforms can kick in and optimize the DAG.
*
* Patterns typically look something like
- * (uaddo A, B)
- * / \
- * Carry Sum
- * | \
- * | (addcarry *, 0, Z)
- * | /
- * \ Carry
- * | /
- * (addcarry X, *, *)
+ * (uaddo A, B)
+ * / \
+ * Carry Sum
+ * | \
+ * | (uaddo_carry *, 0, Z)
+ * | /
+ * \ Carry
+ * | /
+ * (uaddo_carry X, *, *)
*
* But numerous variation exist. Our goal is to identify A, B, X and Z and
* produce a combine with a single path for carry propagation.
*/
-static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
- SDValue X, SDValue Carry0, SDValue Carry1,
- SDNode *N) {
+static SDValue combineUADDO_CARRYDiamond(DAGCombiner &Combiner,
+ SelectionDAG &DAG, SDValue X,
+ SDValue Carry0, SDValue Carry1,
+ SDNode *N) {
if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
return SDValue();
if (Carry1.getOpcode() != ISD::UADDO)
@@ -3382,9 +3384,9 @@ static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
/**
* First look for a suitable Z. It will present itself in the form of
- * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
+ * (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
*/
- if (Carry0.getOpcode() == ISD::ADDCARRY &&
+ if (Carry0.getOpcode() == ISD::UADDO_CARRY &&
isNullConstant(Carry0.getOperand(1))) {
Z = Carry0.getOperand(2);
} else if (Carry0.getOpcode() == ISD::UADDO &&
@@ -3399,26 +3401,27 @@ static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
auto cancelDiamond = [&](SDValue A,SDValue B) {
SDLoc DL(N);
- SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
+ SDValue NewY =
+ DAG.getNode(ISD::UADDO_CARRY, DL, Carry0->getVTList(), A, B, Z);
Combiner.AddToWorklist(NewY.getNode());
- return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
+ return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), X,
DAG.getConstant(0, DL, X.getValueType()),
NewY.getValue(1));
};
/**
- * (uaddo A, B)
- * |
- * Sum
- * |
- * (addcarry *, 0, Z)
+ * (uaddo A, B)
+ * |
+ * Sum
+ * |
+ * (uaddo_carry *, 0, Z)
*/
if (Carry0.getOperand(0) == Carry1.getValue(0)) {
return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
}
/**
- * (addcarry A, 0, Z)
+ * (uaddo_carry A, 0, Z)
* |
* Sum
* |
@@ -3455,12 +3458,12 @@ static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
// | /
// CarryOut = (or *, *)
//
-// And generate ADDCARRY (or SUBCARRY) with two result values:
+// And generate UADDO_CARRY (or USUBO_CARRY) with two result values:
//
-// {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
+// {AddCarrySum, CarryOut} = (uaddo_carry A, B, CarryIn)
//
-// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
-// a single path for carry/borrow out propagation:
+// Our goal is to identify A, B, and CarryIn and produce UADDO_CARRY/USUBO_CARRY
+// with a single path for carry/borrow out propagation.
static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI,
SDValue N0, SDValue N1, SDNode *N) {
SDValue Carry0 = getAsCarry(TLI, N0);
@@ -3493,7 +3496,7 @@ static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI,
return SDValue();
SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);
- unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
+ unsigned NewOp = Opcode == ISD::UADDO ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
return SDValue();
@@ -3529,39 +3532,40 @@ static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI,
return Merged.getValue(1);
}
-SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
- SDNode *N) {
- // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
+SDValue DAGCombiner::visitUADDO_CARRYLike(SDValue N0, SDValue N1,
+ SDValue CarryIn, SDNode *N) {
+ // fold (uaddo_carry (xor a, -1), b, c) -> (usubo_carry b, a, !c) and flip
+ // carry.
if (isBitwiseNot(N0))
if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
SDLoc DL(N);
- SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
+ SDValue Sub = DAG.getNode(ISD::USUBO_CARRY, DL, N->getVTList(), N1,
N0.getOperand(0), NotC);
return CombineTo(
N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1)));
}
// Iff the flag result is dead:
- // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
+ // (uaddo_carry (add|uaddo X, Y), 0, Carry) -> (uaddo_carry X, Y, Carry)
// Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
// or the dependency between the instructions.
if ((N0.getOpcode() == ISD::ADD ||
(N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
N0.getValue(1) != CarryIn)) &&
isNullConstant(N1) && !N->hasAnyUseOfValue(1))
- return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
+ return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(),
N0.getOperand(0), N0.getOperand(1), CarryIn);
/**
- * When one of the addcarry argument is itself a carry, we may be facing
+ * When one of the uaddo_carry argument is itself a carry, we may be facing
* a diamond carry propagation. In which case we try to transform the DAG
* to ensure linear carry propagation if that is possible.
*/
if (auto Y = getAsCarry(TLI, N1)) {
// Because both are carries, Y and Z can be swapped.
- if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
+ if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
return R;
- if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
+ if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
return R;
}
@@ -3985,19 +3989,19 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
}
- // (sub (subcarry X, 0, Carry), Y) -> (subcarry X, Y, Carry)
- if (N0.getOpcode() == ISD::SUBCARRY && isNullConstant(N0.getOperand(1)) &&
+ // (sub (usubo_carry X, 0, Carry), Y) -> (usubo_carry X, Y, Carry)
+ if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) &&
N0.getResNo() == 0 && N0.hasOneUse())
- return DAG.getNode(ISD::SUBCARRY, DL, N0->getVTList(),
+ return DAG.getNode(ISD::USUBO_CARRY, DL, N0->getVTList(),
N0.getOperand(0), N1, N0.getOperand(2));
- if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
- // (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
+ if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) {
+ // (sub Carry, X) -> (uaddo_carry (sub 0, X), 0, Carry)
if (SDValue Carry = getAsCarry(TLI, N0)) {
SDValue X = N1;
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
- return DAG.getNode(ISD::ADDCARRY, DL,
+ return DAG.getNode(ISD::UADDO_CARRY, DL,
DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
Carry);
}
@@ -4149,12 +4153,12 @@ SDValue DAGCombiner::visitSUBE(SDNode *N) {
return SDValue();
}
-SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
+SDValue DAGCombiner::visitUSUBO_CARRY(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);
- // fold (subcarry x, y, false) -> (usubo x, y)
+ // fold (usubo_carry x, y, false) -> (usubo x, y)
if (isNullConstant(CarryIn)) {
if (!LegalOperations ||
TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
@@ -14549,12 +14553,13 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
}
break;
case ISD::ADDE:
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
// (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
- // (trunc addcarry(X, Y, Carry)) -> (addcarry trunc(X), trunc(Y), Carry)
+ // (trunc uaddo_carry(X, Y, Carry)) ->
+ // (uaddo_carry trunc(X), trunc(Y), Carry)
// When the adde's carry is not used.
- // We only do for addcarry before legalize operation
- if (((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) ||
+ // We only do for uaddo_carry before legalize operation
+ if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) ||
TLI.isOperationLegal(N0.getOpcode(), VT)) &&
N0.hasOneUse() && !N0->hasAnyUseOfValue(1)) {
SDLoc DL(N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 8199e5d5a9c18..65e0201d4edd6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3477,13 +3477,13 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// if we were allowed to generate libcalls to division functions of illegal
// type. But we cannot do that.
llvm_unreachable("Cannot expand DIVFIX!");
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: {
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: {
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
SDValue Carry = Node->getOperand(2);
- bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
+ bool IsAdd = Node->getOpcode() == ISD::UADDO_CARRY;
// Initial add of the 2 operands.
unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 4dab62e348233..b80eeedbdf737 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -198,8 +198,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ADDE:
case ISD::SUBE:
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
case ISD::SADDO_CARRY:
case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
@@ -1452,23 +1452,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
-// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
+// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
// the third operand of ADDE/SUBE nodes is carry flag, which
diff ers from
-// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
-SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
+// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
+SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
+ unsigned ResNo) {
if (ResNo == 1)
return PromoteIntRes_Overflow(N);
// We need to sign-extend the operands so the carry value computed by the
// wide operation will be equivalent to the carry value computed by the
// narrow operation.
- // An ADDCARRY can generate carry only if any of the operands has its
+ // An UADDO_CARRY can generate carry only if any of the operands has its
// most significant bit set. Sign extension propagates the most significant
// bit into the higher bits which means the extra bit that the narrow
// addition would need (i.e. the carry) will be propagated through the higher
// bits of the wide addition.
- // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
- // preserved by sign extension.
+ // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
+ // be preserved by sign extension.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
@@ -1697,8 +1698,8 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::SADDO_CARRY:
case ISD::SSUBO_CARRY:
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: Res = PromoteIntOp_ADDSUBO_CARRY(N, OpNo); break;
case ISD::FRAMEADDR:
case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
@@ -2163,7 +2164,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
}
-SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBO_CARRY(SDNode *N, unsigned OpNo) {
assert(OpNo == 2 && "Don't know how to promote this operand!");
SDValue LHS = N->getOperand(0);
@@ -2547,8 +2548,8 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ADDE:
case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
case ISD::SADDO_CARRY:
case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
@@ -2966,7 +2967,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue HiOps[3] = { LHSH, RHSH };
bool HasOpCarry = TLI.isOperationLegalOrCustom(
- N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
+ N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
if (HasOpCarry) {
SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
@@ -2975,13 +2976,13 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
HiOps[2] = Lo.getValue(1);
Hi = DAG.computeKnownBits(HiOps[2]).isZero()
? DAG.getNode(ISD::UADDO, dl, VTList, ArrayRef(HiOps, 2))
- : DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
+ : DAG.getNode(ISD::UADDO_CARRY, dl, VTList, HiOps);
} else {
Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
HiOps[2] = Lo.getValue(1);
Hi = DAG.computeKnownBits(HiOps[2]).isZero()
? DAG.getNode(ISD::USUBO, dl, VTList, ArrayRef(HiOps, 2))
- : DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
+ : DAG.getNode(ISD::USUBO_CARRY, dl, VTList, HiOps);
}
return;
}
@@ -3153,12 +3154,12 @@ void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
ISD::CondCode Cond;
switch(N->getOpcode()) {
case ISD::UADDO:
- CarryOp = ISD::ADDCARRY;
+ CarryOp = ISD::UADDO_CARRY;
NoCarryOp = ISD::ADD;
Cond = ISD::SETULT;
break;
case ISD::USUBO:
- CarryOp = ISD::SUBCARRY;
+ CarryOp = ISD::USUBO_CARRY;
NoCarryOp = ISD::SUB;
Cond = ISD::SETUGT;
break;
@@ -3212,8 +3213,8 @@ void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
ReplaceValueWith(SDValue(N, 1), Ovf);
}
-void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
- SDValue &Lo, SDValue &Hi) {
+void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
// Expand the subcomponents.
SDValue LHSL, LHSH, RHSL, RHSH;
SDLoc dl(N);
@@ -3242,8 +3243,8 @@ void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
// We need to use an unsigned carry op for the lo part.
- unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY
- : ISD::SUBCARRY;
+ unsigned CarryOp =
+ N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
Lo = DAG.getNode(CarryOp, dl, VTList, { LHSL, RHSL, N->getOperand(2) });
Hi = DAG.getNode(N->getOpcode(), dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
@@ -3373,14 +3374,14 @@ void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
return;
}
- // If we have SUBCARRY, use the expanded form of the sra+xor+sub sequence we
- // use in LegalizeDAG. The SUB part of the expansion is based on
- // ExpandIntRes_ADDSUB which also uses SUBCARRY/USUBO after checking that
- // SUBCARRY is LegalOrCustom. Each of the pieces here can be further expanded
- // if needed. Shift expansion has a special case for filling with sign bits
- // so that we will only end up with one SRA.
+ // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
+ // we use in LegalizeDAG. The SUB part of the expansion is based on
+ // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
+ // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
+ // expanded if needed. Shift expansion has a special case for filling with
+ // sign bits so that we will only end up with one SRA.
bool HasSubCarry = TLI.isOperationLegalOrCustom(
- ISD::SUBCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
+ ISD::USUBO_CARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
if (HasSubCarry) {
SDValue Sign = DAG.getNode(
ISD::SRA, dl, NVT, Hi,
@@ -3389,7 +3390,7 @@ void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
Lo = DAG.getNode(ISD::USUBO, dl, VTList, Lo, Sign);
- Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
+ Hi = DAG.getNode(ISD::USUBO_CARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
return;
}
@@ -5153,9 +5154,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
GetExpandedInteger(LHS, LHSLo, LHSHi);
GetExpandedInteger(RHS, RHSLo, RHSHi);
- // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
+ // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
- SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
+ SDValue LowCmp =
+ DAG.getNode(ISD::USUBO_CARRY, dl, VTList, LHSLo, RHSLo, Carry);
return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
LowCmp.getValue(1), Cond);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f5cce12a39299..f4896cd1f09ad 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -347,7 +347,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_SRL(SDNode *N);
SDValue PromoteIntRes_TRUNCATE(SDNode *N);
SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
- SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_UADDSUBO_CARRY(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_SADDSUBO_CARRY(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_UNDEF(SDNode *N);
SDValue PromoteIntRes_VAARG(SDNode *N);
@@ -396,7 +396,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
- SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_ADDSUBO_CARRY(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_FIX(SDNode *N);
@@ -449,7 +449,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
- void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_UADDSUBO_CARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SADDSUBO_CARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3fff6e2f39cbf..9b0d53c920ce4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3637,7 +3637,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
case ISD::USUBO:
case ISD::SSUBO:
- case ISD::SUBCARRY:
+ case ISD::USUBO_CARRY:
case ISD::SSUBO_CARRY:
if (Op.getResNo() == 1) {
// If we know the result of a setcc has the top bits zero, use this info.
@@ -3654,7 +3654,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
"We only compute knownbits for the
diff erence here.");
// TODO: Compute influence of the carry operand.
- if (Opcode == ISD::SUBCARRY || Opcode == ISD::SSUBO_CARRY)
+ if (Opcode == ISD::USUBO_CARRY || Opcode == ISD::SSUBO_CARRY)
break;
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
@@ -3665,7 +3665,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
case ISD::UADDO:
case ISD::SADDO:
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
case ISD::SADDO_CARRY:
if (Op.getResNo() == 1) {
// If we know the result of a setcc has the top bits zero, use this info.
@@ -3681,12 +3681,12 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
case ISD::ADDE: {
assert(Op.getResNo() == 0 && "We only compute knownbits for the sum here.");
- // With ADDE and ADDCARRY, a carry bit may be added in.
+ // With ADDE and UADDO_CARRY, a carry bit may be added in.
KnownBits Carry(1);
if (Opcode == ISD::ADDE)
// Can't track carry from glue, set carry to unknown.
Carry.resetAll();
- else if (Opcode == ISD::ADDCARRY || Opcode == ISD::SADDO_CARRY)
+ else if (Opcode == ISD::UADDO_CARRY || Opcode == ISD::SADDO_CARRY)
// TODO: Compute known bits for the carry operand. Not sure if it is worth
// the trouble (how often will we find a known carry bit). And I haven't
// tested this very much yet, but something like this might work:
@@ -4269,11 +4269,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::SADDO:
case ISD::UADDO:
case ISD::SADDO_CARRY:
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
case ISD::SSUBO:
case ISD::USUBO:
case ISD::SSUBO_CARRY:
- case ISD::SUBCARRY:
+ case ISD::USUBO_CARRY:
case ISD::SMULO:
case ISD::UMULO:
if (Op.getResNo() != 1)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index f6d4ad1b46e90..14f9acbee7e37 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -309,7 +309,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::CARRY_FALSE: return "carry_false";
case ISD::ADDC: return "addc";
case ISD::ADDE: return "adde";
- case ISD::ADDCARRY: return "addcarry";
+ case ISD::UADDO_CARRY: return "uaddo_carry";
case ISD::SADDO_CARRY: return "saddo_carry";
case ISD::SADDO: return "saddo";
case ISD::UADDO: return "uaddo";
@@ -319,7 +319,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::UMULO: return "umulo";
case ISD::SUBC: return "subc";
case ISD::SUBE: return "sube";
- case ISD::SUBCARRY: return "subcarry";
+ case ISD::USUBO_CARRY: return "usubo_carry";
case ISD::SSUBO_CARRY: return "ssubo_carry";
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5763d4bd0b4a7..dc2475bee1400 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -7222,7 +7222,7 @@ bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl,
Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
Merge(Lo, Hi));
else
- Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
+ Next = DAG.getNode(ISD::UADDO_CARRY, dl, DAG.getVTList(VT, BoolType), Next,
Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType));
SDValue Carry = Next.getValue(1);
@@ -7236,7 +7236,7 @@ bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl,
Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
Carry);
else
- Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
+ Hi = DAG.getNode(ISD::UADDO_CARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
Zero, Carry);
Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
@@ -7378,13 +7378,13 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
}
- // Use addcarry if we can, otherwise use a compare to detect overflow.
+ // Use uaddo_carry if we can, otherwise use a compare to detect overflow.
EVT SetCCType =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), HiLoVT);
- if (isOperationLegalOrCustom(ISD::ADDCARRY, HiLoVT)) {
+ if (isOperationLegalOrCustom(ISD::UADDO_CARRY, HiLoVT)) {
SDVTList VTList = DAG.getVTList(HiLoVT, SetCCType);
Sum = DAG.getNode(ISD::UADDO, dl, VTList, LL, LH);
- Sum = DAG.getNode(ISD::ADDCARRY, dl, VTList, Sum,
+ Sum = DAG.getNode(ISD::UADDO_CARRY, dl, VTList, Sum,
DAG.getConstant(0, dl, HiLoVT), Sum.getValue(1));
} else {
Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
@@ -9935,8 +9935,8 @@ void TargetLowering::expandUADDSUBO(
SDValue RHS = Node->getOperand(1);
bool IsAdd = Node->getOpcode() == ISD::UADDO;
- // If ADD/SUBCARRY is legal, use that instead.
- unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
+ // If UADDO_CARRY/SUBO_CARRY is legal, use that instead.
+ unsigned OpcCarry = IsAdd ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 6d006ff6081b4..1b31ff33ddbc7 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -821,8 +821,8 @@ void TargetLoweringBase::initActions() {
ISD::SMULO, ISD::UMULO},
VT, Expand);
- // ADDCARRY operations default to expand
- setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY, ISD::SETCCCARRY,
+ // Carry-using overflow operations default to expand.
+ setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
VT, Expand);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a417b02cbb86b..cf15231f4f15c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -645,10 +645,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::UMULO, MVT::i32, Custom);
setOperationAction(ISD::UMULO, MVT::i64, Custom);
- setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
- setOperationAction(ISD::ADDCARRY, MVT::i64, Custom);
- setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
- setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);
+ setOperationAction(ISD::UADDO_CARRY, MVT::i32, Custom);
+ setOperationAction(ISD::UADDO_CARRY, MVT::i64, Custom);
+ setOperationAction(ISD::USUBO_CARRY, MVT::i32, Custom);
+ setOperationAction(ISD::USUBO_CARRY, MVT::i64, Custom);
setOperationAction(ISD::SADDO_CARRY, MVT::i32, Custom);
setOperationAction(ISD::SADDO_CARRY, MVT::i64, Custom);
setOperationAction(ISD::SSUBO_CARRY, MVT::i32, Custom);
@@ -3683,8 +3683,8 @@ static SDValue overflowFlagToValue(SDValue Glue, EVT VT, SelectionDAG &DAG) {
// This lowering is inefficient, but it will get cleaned up by
// `foldOverflowCheck`
-static SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG, unsigned Opcode,
- bool IsSigned) {
+static SDValue lowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG,
+ unsigned Opcode, bool IsSigned) {
EVT VT0 = Op.getValue(0).getValueType();
EVT VT1 = Op.getValue(1).getValueType();
@@ -5760,14 +5760,14 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
return LowerVACOPY(Op, DAG);
case ISD::VAARG:
return LowerVAARG(Op, DAG);
- case ISD::ADDCARRY:
- return lowerADDSUBCARRY(Op, DAG, AArch64ISD::ADCS, false /*unsigned*/);
- case ISD::SUBCARRY:
- return lowerADDSUBCARRY(Op, DAG, AArch64ISD::SBCS, false /*unsigned*/);
+ case ISD::UADDO_CARRY:
+ return lowerADDSUBO_CARRY(Op, DAG, AArch64ISD::ADCS, false /*unsigned*/);
+ case ISD::USUBO_CARRY:
+ return lowerADDSUBO_CARRY(Op, DAG, AArch64ISD::SBCS, false /*unsigned*/);
case ISD::SADDO_CARRY:
- return lowerADDSUBCARRY(Op, DAG, AArch64ISD::ADCS, true /*signed*/);
+ return lowerADDSUBO_CARRY(Op, DAG, AArch64ISD::ADCS, true /*signed*/);
case ISD::SSUBO_CARRY:
- return lowerADDSUBCARRY(Op, DAG, AArch64ISD::SBCS, true /*signed*/);
+ return lowerADDSUBO_CARRY(Op, DAG, AArch64ISD::SBCS, true /*signed*/);
case ISD::SADDO:
case ISD::UADDO:
case ISD::SSUBO:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 9e3477cf9c272..b50687b643951 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -527,8 +527,8 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
SelectADD_SUB_I64(N);
return;
}
- case ISD::ADDCARRY:
- case ISD::SUBCARRY:
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY:
if (N->getValueType(0) != MVT::i32)
break;
@@ -808,7 +808,7 @@ SDValue AMDGPUDAGToDAGISel::getMaterializedScalarImm32(int64_t Val,
return SDValue(Mov, 0);
}
-// FIXME: Should only handle addcarry/subcarry
+// FIXME: Should only handle uaddo_carry/usubo_carry
void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
SDLoc DL(N);
SDValue LHS = N->getOperand(0);
@@ -885,15 +885,15 @@ void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
SDValue CI = N->getOperand(2);
if (N->isDivergent()) {
- unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64
- : AMDGPU::V_SUBB_U32_e64;
+ unsigned Opc = N->getOpcode() == ISD::UADDO_CARRY ? AMDGPU::V_ADDC_U32_e64
+ : AMDGPU::V_SUBB_U32_e64;
CurDAG->SelectNodeTo(
N, Opc, N->getVTList(),
{LHS, RHS, CI,
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
} else {
- unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO
- : AMDGPU::S_SUB_CO_PSEUDO;
+ unsigned Opc = N->getOpcode() == ISD::UADDO_CARRY ? AMDGPU::S_ADD_CO_PSEUDO
+ : AMDGPU::S_SUB_CO_PSEUDO;
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), {LHS, RHS, CI});
}
}
@@ -908,8 +908,8 @@ void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;
++UI)
if (UI.getUse().getResNo() == 1) {
- if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) ||
- (!IsAdd && (UI->getOpcode() != ISD::SUBCARRY))) {
+ if ((IsAdd && (UI->getOpcode() != ISD::UADDO_CARRY)) ||
+ (!IsAdd && (UI->getOpcode() != ISD::USUBO_CARRY))) {
IsVALU = true;
break;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 7c25eeaddc6af..79f31c2350733 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1963,9 +1963,9 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
SDValue Mulhi1_Lo, Mulhi1_Hi;
std::tie(Mulhi1_Lo, Mulhi1_Hi) =
DAG.SplitScalar(Mulhi1, DL, HalfVT, HalfVT);
- SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
+ SDValue Add1_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Lo,
Mulhi1_Lo, Zero1);
- SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
+ SDValue Add1_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Hi,
Mulhi1_Hi, Add1_Lo.getValue(1));
SDValue Add1 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
@@ -1976,9 +1976,9 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
SDValue Mulhi2_Lo, Mulhi2_Hi;
std::tie(Mulhi2_Lo, Mulhi2_Hi) =
DAG.SplitScalar(Mulhi2, DL, HalfVT, HalfVT);
- SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
+ SDValue Add2_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Lo,
Mulhi2_Lo, Zero1);
- SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Hi,
+ SDValue Add2_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Hi,
Mulhi2_Hi, Add2_Lo.getValue(1));
SDValue Add2 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
@@ -1989,9 +1989,9 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
SDValue Mul3_Lo, Mul3_Hi;
std::tie(Mul3_Lo, Mul3_Hi) = DAG.SplitScalar(Mul3, DL, HalfVT, HalfVT);
- SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
+ SDValue Sub1_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Lo,
Mul3_Lo, Zero1);
- SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
+ SDValue Sub1_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Hi,
Mul3_Hi, Sub1_Lo.getValue(1));
SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
SDValue Sub1 = DAG.getBitcast(VT,
@@ -2009,11 +2009,11 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
// potential endif to substitute PHIs.
// if C3 != 0 ...
- SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
+ SDValue Sub2_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Lo,
RHS_Lo, Zero1);
- SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
+ SDValue Sub2_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Mi,
RHS_Hi, Sub1_Lo.getValue(1));
- SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
+ SDValue Sub2_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi,
Zero, Sub2_Lo.getValue(1));
SDValue Sub2 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
@@ -2029,11 +2029,11 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
// if (C6 != 0)
SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
- SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
+ SDValue Sub3_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Lo,
RHS_Lo, Zero1);
- SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
+ SDValue Sub3_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi,
RHS_Hi, Sub2_Lo.getValue(1));
- SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
+ SDValue Sub3_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub3_Mi,
Zero, Sub3_Lo.getValue(1));
SDValue Sub3 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 4e4634123f89f..ef12aa920dd35 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -244,13 +244,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Legal);
- setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i32, Legal);
+ setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY}, MVT::i32, Legal);
setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}, MVT::i64,
Expand);
#if 0
- setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i64, Legal);
+ setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY}, MVT::i64, Legal);
#endif
// We only support LOAD/STORE and vector manipulation ops for vectors
@@ -744,9 +744,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Custom);
setTargetDAGCombine({ISD::ADD,
- ISD::ADDCARRY,
+ ISD::UADDO_CARRY,
ISD::SUB,
- ISD::SUBCARRY,
+ ISD::USUBO_CARRY,
ISD::FADD,
ISD::FSUB,
ISD::FMINNUM,
@@ -11268,11 +11268,11 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
return SDValue();
- // add x, zext (setcc) => addcarry x, 0, setcc
- // add x, sext (setcc) => subcarry x, 0, setcc
+ // add x, zext (setcc) => uaddo_carry x, 0, setcc
+ // add x, sext (setcc) => usubo_carry x, 0, setcc
unsigned Opc = LHS.getOpcode();
if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||
- Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY)
+ Opc == ISD::ANY_EXTEND || Opc == ISD::UADDO_CARRY)
std::swap(RHS, LHS);
Opc = RHS.getOpcode();
@@ -11288,15 +11288,15 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
break;
SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
- Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
+ Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::USUBO_CARRY : ISD::UADDO_CARRY;
return DAG.getNode(Opc, SL, VTList, Args);
}
- case ISD::ADDCARRY: {
- // add x, (addcarry y, 0, cc) => addcarry x, y, cc
+ case ISD::UADDO_CARRY: {
+ // add x, (uaddo_carry y, 0, cc) => uaddo_carry x, y, cc
if (!isNullConstant(RHS.getOperand(1)))
break;
SDValue Args[] = { LHS, RHS.getOperand(0), RHS.getOperand(2) };
- return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
+ return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), RHS->getVTList(), Args);
}
}
return SDValue();
@@ -11314,8 +11314,8 @@ SDValue SITargetLowering::performSubCombine(SDNode *N,
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
- // sub x, zext (setcc) => subcarry x, 0, setcc
- // sub x, sext (setcc) => addcarry x, 0, setcc
+ // sub x, zext (setcc) => usubo_carry x, 0, setcc
+ // sub x, sext (setcc) => uaddo_carry x, 0, setcc
unsigned Opc = RHS.getOpcode();
switch (Opc) {
default: break;
@@ -11329,18 +11329,18 @@ SDValue SITargetLowering::performSubCombine(SDNode *N,
break;
SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
- Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY;
+ Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
return DAG.getNode(Opc, SL, VTList, Args);
}
}
- if (LHS.getOpcode() == ISD::SUBCARRY) {
- // sub (subcarry x, 0, cc), y => subcarry x, y, cc
+ if (LHS.getOpcode() == ISD::USUBO_CARRY) {
+ // sub (usubo_carry x, 0, cc), y => usubo_carry x, y, cc
auto C = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
if (!C || !C->isZero())
return SDValue();
SDValue Args[] = { LHS.getOperand(0), RHS, LHS.getOperand(2) };
- return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
+ return DAG.getNode(ISD::USUBO_CARRY, SDLoc(N), LHS->getVTList(), Args);
}
return SDValue();
}
@@ -11357,12 +11357,12 @@ SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,
SelectionDAG &DAG = DCI.DAG;
SDValue LHS = N->getOperand(0);
- // addcarry (add x, y), 0, cc => addcarry x, y, cc
- // subcarry (sub x, y), 0, cc => subcarry x, y, cc
+ // uaddo_carry (add x, y), 0, cc => uaddo_carry x, y, cc
+ // usubo_carry (sub x, y), 0, cc => usubo_carry x, y, cc
unsigned LHSOpc = LHS.getOpcode();
unsigned Opc = N->getOpcode();
- if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) ||
- (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
+ if ((LHSOpc == ISD::ADD && Opc == ISD::UADDO_CARRY) ||
+ (LHSOpc == ISD::SUB && Opc == ISD::USUBO_CARRY)) {
SDValue Args[] = { LHS.getOperand(0), LHS.getOperand(1), N->getOperand(2) };
return DAG.getNode(Opc, SDLoc(N), N->getVTList(), Args);
}
@@ -11714,8 +11714,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
return performAddCombine(N, DCI);
case ISD::SUB:
return performSubCombine(N, DCI);
- case ISD::ADDCARRY:
- case ISD::SUBCARRY:
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY:
return performAddCarrySubCarryCombine(N, DCI);
case ISD::FADD:
return performFAddCombine(N, DCI);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index a0058e484f821..ca86b00e0489b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1132,8 +1132,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SSUBO, MVT::i32, Custom);
setOperationAction(ISD::USUBO, MVT::i32, Custom);
- setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
- setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
+ setOperationAction(ISD::UADDO_CARRY, MVT::i32, Custom);
+ setOperationAction(ISD::USUBO_CARRY, MVT::i32, Custom);
if (Subtarget->hasDSP()) {
setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
@@ -6888,7 +6888,7 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
- // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
+ // ARMISD::SUBE expects a carry not a borrow like ISD::USUBO_CARRY so we
// have to invert the carry first.
Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
DAG.getConstant(1, DL, MVT::i32), Carry);
@@ -9791,7 +9791,7 @@ static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG,
return N0;
}
-static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
+static SDValue LowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) {
SDNode *N = Op.getNode();
EVT VT = N->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
@@ -9801,7 +9801,7 @@ static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
SDLoc DL(Op);
SDValue Result;
- if (Op.getOpcode() == ISD::ADDCARRY) {
+ if (Op.getOpcode() == ISD::UADDO_CARRY) {
// This converts the boolean value carry into the carry flag.
Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
@@ -9812,7 +9812,7 @@ static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
// Now convert the carry flag into a boolean value.
Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
} else {
- // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
+ // ARMISD::SUBE expects a carry not a borrow like ISD::USUBO_CARRY so we
// have to invert the carry first.
Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
DAG.getConstant(1, DL, MVT::i32), Carry);
@@ -9826,7 +9826,7 @@ static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
// Now convert the carry flag into a boolean value.
Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
// But the carry returned by ARMISD::SUBE is not a borrow as expected
- // by ISD::SUBCARRY, so compute 1 - C.
+ // by ISD::USUBO_CARRY, so compute 1 - C.
Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
DAG.getConstant(1, DL, MVT::i32), Carry);
}
@@ -10544,8 +10544,9 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
return LowerDIV_Windows(Op, DAG, /* Signed */ false);
return LowerUDIV(Op, DAG, Subtarget);
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY:
+ return LowerUADDSUBO_CARRY(Op, DAG);
case ISD::SADDO:
case ISD::SSUBO:
return LowerSignedALUO(Op, DAG);
@@ -18373,23 +18374,23 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
DAG.getConstant(5, dl, MVT::i32));
} else {
// CMOV 0, 1, ==, (CMPZ x, y) ->
- // (ADDCARRY (SUB x, y), t:0, t:1)
- // where t = (SUBCARRY 0, (SUB x, y), 0)
+ // (UADDO_CARRY (SUB x, y), t:0, t:1)
+ // where t = (USUBO_CARRY 0, (SUB x, y), 0)
//
- // The SUBCARRY computes 0 - (x - y) and this will give a borrow when
+ // The USUBO_CARRY computes 0 - (x - y) and this will give a borrow when
// x != y. In other words, a carry C == 1 when x == y, C == 0
// otherwise.
- // The final ADDCARRY computes
+ // The final UADDO_CARRY computes
// x - y + (0 - (x - y)) + C == C
SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
SDValue Neg = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, Sub);
- // ISD::SUBCARRY returns a borrow but we want the carry here
+ // ISD::USUBO_CARRY returns a borrow but we want the carry here
// actually.
SDValue Carry =
DAG.getNode(ISD::SUB, dl, MVT::i32,
DAG.getConstant(1, dl, MVT::i32), Neg.getValue(1));
- Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry);
+ Res = DAG.getNode(ISD::UADDO_CARRY, dl, VTs, Sub, Neg, Carry);
}
} else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
(!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) {
@@ -18424,14 +18425,14 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
// (z == 2 ^ K).
// CMOV (SUBS x, y), z, !=, (SUBS x, y):1 ->
// t1 = (USUBO (SUB x, y), 1)
- // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
+ // t2 = (USUBO_CARRY (SUB x, y), t1:0, t1:1)
// Result = if K != 0 then (SHL t2:0, K) else t2:0
//
// This also handles the special case of comparing against zero; it's
// essentially, the same pattern, except there's no SUBS:
// CMOV x, z, !=, (CMPZ x, 0) ->
// t1 = (USUBO x, 1)
- // t2 = (SUBCARRY x, t1:0, t1:1)
+ // t2 = (USUBO_CARRY x, t1:0, t1:1)
// Result = if K != 0 then (SHL t2:0, K) else t2:0
const APInt *TrueConst;
if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&
@@ -18444,7 +18445,8 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
if (ShiftAmount)
TrueVal = DAG.getConstant(1, dl, VT);
SDValue Subc = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, TrueVal);
- Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1));
+ Res = DAG.getNode(ISD::USUBO_CARRY, dl, VTs, FalseVal, Subc,
+ Subc.getValue(1));
if (ShiftAmount)
Res = DAG.getNode(ISD::SHL, dl, VT, Res,
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 09c2d5161aba0..702053e02332e 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -74,10 +74,10 @@ void CSKYDAGToDAGISel::Select(SDNode *N) {
switch (Opcode) {
default:
break;
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
IsSelected = selectAddCarry(N);
break;
- case ISD::SUBCARRY:
+ case ISD::USUBO_CARRY:
IsSelected = selectSubCarry(N);
break;
case ISD::GLOBAL_OFFSET_TABLE: {
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index a08ba27f6ec36..487b9d9d1388b 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -51,8 +51,8 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
}
- setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
- setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
+ setOperationAction(ISD::UADDO_CARRY, MVT::i32, Legal);
+ setOperationAction(ISD::USUBO_CARRY, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::SREM, MVT::i32, Expand);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 1838b95f2b79a..f826f613b2846 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1545,15 +1545,15 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
// Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
// but they only operate on i64.
for (MVT VT : MVT::integer_valuetypes()) {
- setOperationAction(ISD::UADDO, VT, Custom);
- setOperationAction(ISD::USUBO, VT, Custom);
- setOperationAction(ISD::SADDO, VT, Expand);
- setOperationAction(ISD::SSUBO, VT, Expand);
- setOperationAction(ISD::ADDCARRY, VT, Expand);
- setOperationAction(ISD::SUBCARRY, VT, Expand);
+ setOperationAction(ISD::UADDO, VT, Custom);
+ setOperationAction(ISD::USUBO, VT, Custom);
+ setOperationAction(ISD::SADDO, VT, Expand);
+ setOperationAction(ISD::SSUBO, VT, Expand);
+ setOperationAction(ISD::UADDO_CARRY, VT, Expand);
+ setOperationAction(ISD::USUBO_CARRY, VT, Expand);
}
- setOperationAction(ISD::ADDCARRY, MVT::i64, Custom);
- setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);
+ setOperationAction(ISD::UADDO_CARRY, MVT::i64, Custom);
+ setOperationAction(ISD::USUBO_CARRY, MVT::i64, Custom);
setOperationAction(ISD::CTLZ, MVT::i8, Promote);
setOperationAction(ISD::CTLZ, MVT::i16, Promote);
@@ -3263,13 +3263,13 @@ HexagonTargetLowering::LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
}
-SDValue
-HexagonTargetLowering::LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const {
+SDValue HexagonTargetLowering::LowerUAddSubOCarry(SDValue Op,
+ SelectionDAG &DAG) const {
const SDLoc &dl(Op);
unsigned Opc = Op.getOpcode();
SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
- if (Opc == ISD::ADDCARRY)
+ if (Opc == ISD::UADDO_CARRY)
return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
{ X, Y, C });
@@ -3342,8 +3342,8 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::STORE: return LowerStore(Op, DAG);
case ISD::UADDO:
case ISD::USUBO: return LowerUAddSubO(Op, DAG);
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: return LowerUAddSubOCarry(Op, DAG);
case ISD::SRA:
case ISD::SHL:
case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index fc7072d14ccdd..64fa8933cea52 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -200,7 +200,7 @@ class HexagonTargetLowering : public TargetLowering {
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index a07a11a7ce930..256c0fa036b4d 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -186,8 +186,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::USUBO, VT, Custom);
// Support carry in as value rather than glue.
- setOperationAction(ISD::ADDCARRY, VT, Custom);
- setOperationAction(ISD::SUBCARRY, VT, Custom);
+ setOperationAction(ISD::UADDO_CARRY, VT, Custom);
+ setOperationAction(ISD::USUBO_CARRY, VT, Custom);
// Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
// stores, putting a serialization instruction after the stores.
@@ -3995,20 +3995,20 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
}
static bool isAddCarryChain(SDValue Carry) {
- while (Carry.getOpcode() == ISD::ADDCARRY)
+ while (Carry.getOpcode() == ISD::UADDO_CARRY)
Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::UADDO;
}
static bool isSubBorrowChain(SDValue Carry) {
- while (Carry.getOpcode() == ISD::SUBCARRY)
+ while (Carry.getOpcode() == ISD::USUBO_CARRY)
Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::USUBO;
}
-// Lower ADDCARRY/SUBCARRY nodes.
-SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
- SelectionDAG &DAG) const {
+// Lower UADDO_CARRY/USUBO_CARRY nodes.
+SDValue SystemZTargetLowering::lowerUADDSUBO_CARRY(SDValue Op,
+ SelectionDAG &DAG) const {
SDNode *N = Op.getNode();
MVT VT = N->getSimpleValueType(0);
@@ -4027,7 +4027,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!");
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
if (!isAddCarryChain(Carry))
return SDValue();
@@ -4035,7 +4035,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
CCValid = SystemZ::CCMASK_LOGICAL;
CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
break;
- case ISD::SUBCARRY:
+ case ISD::USUBO_CARRY:
if (!isSubBorrowChain(Carry))
return SDValue();
@@ -5741,9 +5741,9 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
case ISD::UADDO:
case ISD::USUBO:
return lowerXALUO(Op, DAG);
- case ISD::ADDCARRY:
- case ISD::SUBCARRY:
- return lowerADDSUBCARRY(Op, DAG);
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY:
+ return lowerUADDSUBO_CARRY(Op, DAG);
case ISD::OR:
return lowerOR(Op, DAG);
case ISD::CTPOP:
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 8c98eb80f9ee0..7f6e25ccf6f7a 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -658,7 +658,7 @@ class SystemZTargetLowering : public TargetLowering {
SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index cd6bf0c3729db..e2149951aff0e 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -646,7 +646,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
case X86ISD::XOR:
case X86ISD::OR:
case ISD::ADD:
- case ISD::ADDCARRY:
+ case ISD::UADDO_CARRY:
case ISD::AND:
case ISD::OR:
case ISD::XOR: {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2db70d270f5f7..0ff432f62945f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2331,8 +2331,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UMULO, VT, Custom);
// Support carry in as value rather than glue.
- setOperationAction(ISD::ADDCARRY, VT, Custom);
- setOperationAction(ISD::SUBCARRY, VT, Custom);
+ setOperationAction(ISD::UADDO_CARRY, VT, Custom);
+ setOperationAction(ISD::USUBO_CARRY, VT, Custom);
setOperationAction(ISD::SETCCCARRY, VT, Custom);
setOperationAction(ISD::SADDO_CARRY, VT, Custom);
setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
@@ -33358,7 +33358,7 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG,
return Swap.getValue(1);
}
-static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
+static SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) {
SDNode *N = Op.getNode();
MVT VT = N->getSimpleValueType(0);
unsigned Opc = Op.getOpcode();
@@ -33376,7 +33376,7 @@ static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
Carry = DAG.getNode(X86ISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32),
Carry, DAG.getAllOnesConstant(DL, CarryVT));
- bool IsAdd = Opc == ISD::ADDCARRY || Opc == ISD::SADDO_CARRY;
+ bool IsAdd = Opc == ISD::UADDO_CARRY || Opc == ISD::SADDO_CARRY;
SDValue Sum = DAG.getNode(IsAdd ? X86ISD::ADC : X86ISD::SBB, DL, VTs,
Op.getOperand(0), Op.getOperand(1),
Carry.getValue(1));
@@ -33951,8 +33951,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
case ISD::SADDO_CARRY:
case ISD::SSUBO_CARRY:
- case ISD::ADDCARRY:
- case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
+ case ISD::UADDO_CARRY:
+ case ISD::USUBO_CARRY: return LowerADDSUBO_CARRY(Op, DAG);
case ISD::ADD:
case ISD::SUB: return lowerAddSub(Op, DAG, Subtarget);
case ISD::UADDSAT:
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