[PATCH] D149383: [SelectionDAG][WIP] Add support for evaluating SetCC based on knownbits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/cmp-const-max.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
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regenerate + commit this file and rebase to show the diffs from the patch


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Comment at: llvm/test/CodeGen/ARM/sub-cmp-peephole.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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regenerate this file first so you show any diffs


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Comment at: llvm/test/CodeGen/X86/fold-rmw-ops.ll:1372
   store i64 %or, ptr @g64
   %cond = icmp eq i64 %or, 0
   br i1 %cond, label %a, label %b
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comparing against zero in all these or-with-imm tests just seems to be a copy+paste from the other logic ops in this file - maybe change it to something that isn't constant foldable (test for -ve?)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149383/new/

https://reviews.llvm.org/D149383