[PATCH] D147408: [AMDGPU] Iterative scan implementation for atomic optimizer.

[Pravin Jagtap via Phabricator via llvm-commits]

pravinjagtap added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll:459-462
+; GFX8-NEXT:    s_ff1_i32_b32 s5, s3
+; GFX8-NEXT:    s_ff1_i32_b32 s6, s2
+; GFX8-NEXT:    s_add_i32 s5, s5, 32
+; GFX8-NEXT:    s_min_u32 s5, s6, s5
----------------
foad wrote:
> Not your fault, but we really ought to be able to select s_ff1_i32_b64 here.
> Not your fault, but we really ought to be able to select s_ff1_i32_b64 here.

I am not sure how to address this. May be, we need to teach ISel this specific pattern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147408/new/

https://reviews.llvm.org/D147408