[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland marked an inline comment as done.
michaelmaitland added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:181
+                                       FeatureStdExtZvfh,
+                                       FeatureStdExtZba,
+                                       FeatureStdExtZbb],
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craig.topper wrote:
> This makes the patch dependent on adding sifive-x280
Added parent revision.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149497/new/

https://reviews.llvm.org/D149497