[PATCH] D149495: Add sifive-x280 processor and support V extenstion in SiFive7

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland created this revision.
michaelmaitland added reviewers: craig.topper, kito-cheng, reames, pcwang-thead.
Herald added subscribers: luke, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
michaelmaitland requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Add x280 processor that uses SiFive7 with vector extension.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149495

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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