[PATCH] D149488: [RISCV] Use AMOSWAP for 32 and 64-bit atomic stores

[Paul Kirth via Phabricator via llvm-commits]

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These are expected to be more performant and comply with the
recommendations in Hans Boehm's proposal for changes to table A.6 of the
unprivileged spec and the RISC-V psABI. Further details can be found in
the psABI proposal:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378.

The proposal suggests that as an optimization, the memory_order_seq_cst
store mapping may be replaced by the following for 32- and 64-bit
operands:

  amoswap.rl{w|d};

Depends on: D149486 <https://reviews.llvm.org/D149486>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149488

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/atomic-load-store.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll

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