[PATCH] D149223: [PowerPC] Look through OR, AND, XOR instructions when checking a clear.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 518023.
stefanp added a comment.

Fixed the operands because they were not supposed to be the same.
Added the record forms.
Fixed the typo of having two XOR8 and no OR8.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149223/new/

https://reviews.llvm.org/D149223

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll


Index: llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
+++ llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
@@ -15,7 +15,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    xor r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor:
@@ -43,7 +42,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    xor r4, r5, r4
 ; 64BIT-NEXT:    xor r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor2:
@@ -74,7 +72,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or:
@@ -102,7 +99,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    or r4, r5, r4
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or2:
@@ -133,7 +129,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    and r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and:
@@ -161,7 +156,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    and r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and2:
@@ -196,7 +190,6 @@
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    xor r4, r4, r6
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixed:
@@ -236,7 +229,6 @@
 ; 64BIT-NEXT:    and r5, r6, r5
 ; 64BIT-NEXT:    xor r3, r5, r3
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 48
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixedtype:
Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -219,6 +219,20 @@
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
+  if (Opcode == PPC::AND || Opcode == PPC::AND8 || Opcode == PPC::AND_rec ||
+      Opcode == PPC::AND8_rec)
+    return std::max(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI));
+
+  if (Opcode == PPC::OR || Opcode == PPC::OR8 || Opcode == PPC::XOR ||
+      Opcode == PPC::XOR8 || Opcode == PPC::OR_rec ||
+      Opcode == PPC::OR8_rec || Opcode == PPC::XOR_rec ||
+      Opcode == PPC::XOR8_rec)
+    return std::min(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI));
+
   if (TII->isZeroExtended(Reg, MRI))
     return 32;
 


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