[PATCH] D149263: [RISCV] Use vslide1down idiom for generic build_vector

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D149263#4306115 <https://reviews.llvm.org/D149263#4306115>, @craig.topper wrote:

>> vfslide1down ISD notes being in place
>
> Was that supposed to be "nodes" instead of "notes"?

Yep.  Will update.



================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll:84-87
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
----------------
luke wrote:
> This is interesting. The legalised DAG must be something like `build_vector <a4, a3, a2, a1, a0, undef, undef, undef>`.
> Is there a potential combine we could do here to convert `n` nested `(vslide1down.vx v, undef)` into `(vslidedown.vi v, n)`?
This needs a bit of care.  The advantage of using the vslide1down idiom is that we can use the same VL throughout and thus avoid vsetvli toggles.  We may be able to make something like this work, but it requires a bit of care.

Another idea in the same vein is to do a smaller build vector of only the undef prefix and then slide into result vector.  

This particular case - with undef forming a suffix - could be handled by explicitly decreasing VL and only sliding in the non-undef prefix.  This works out to be the same as the former idea.  


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