[PATCH] D149369: [RISCV] Consolidate legality checking for strided load/store [nfc]
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 28 08:07:09 PDT 2023
reames added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11255
// Get the widened scalar type, e.g. v4i8 -> i64
unsigned WideScalarBitWidth =
BaseLdVT.getScalarSizeInBits() * BaseLdVT.getVectorNumElements();
----------------
luke wrote:
> craig.topper wrote:
> > Is WideScalarBitWidth guaranteed to be a valid MVT? Like can we get i256, i512, i1024, etc. here?
> I presume if it's not then WideVecVT won't be legal below and we'll fail the legality check
This was my reasoning as well.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149369/new/
https://reviews.llvm.org/D149369
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