[PATCH] D143898: [CodeGenPrepare] Relax conditions for folding addressing mode into loads/stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

For constructs like the given testcase, you don't need to reason about whether it's profitable to fold into a call; cloning a GEP into both sides of an if-else doesn't actually increase execution time, so it's obviously profitable even if you can only fold it on one side of the if-else.  Can you add some examples that actually require predicting whether the GEP is as cheap as a mov, and the argument is passed in a register?



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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:3178
+                                       const AddrMode &AM) const {
+    return AM.HasBaseReg && AM.BaseGV == nullptr && AM.Scale == 0 && AM.BaseOffs == 0;
+  }
----------------
In this case, the addressing mode doesn't actually represent any computation, so it isn't relevant for this transform; when do you expect it to become relevant?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:24528
+
+  if (ArgNo > 7 || AM.BaseGV || !AM.HasBaseReg)
+    return false;
----------------
Counting arguments like this won't do what you want if there are arguments which are passed in multiple registers.


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  https://reviews.llvm.org/D143898/new/

https://reviews.llvm.org/D143898