[PATCH] D149375: [RISCV] Introduce unaligned-vector-mem feature

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

> While making this change, I realized that we actually *do* support unaligned vector loads and stores of all types via conversion to i8 element type. For contiguous loads and stores, we actually already implement this in the backend - though we don't tell the optimizer that. For indexed, lowering to i8 requires complicated addressing. For indexed and segmented, we'd have to use indexed. All around, doesn't seem worthwhile pursuing, but makes for an interesting observation.

I don't think we support unaligned for contiguous masked load/store or VP load/store.


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  https://reviews.llvm.org/D149375/new/

https://reviews.llvm.org/D149375