[PATCH] D149375: [RISCV] Introduce unaligned-vector-mem feature

[Philip Reames via Phabricator via llvm-commits]

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This allows us to model and thus test transforms which are legal only when a vector load with less than element alignment are supported.  This was originally part of D126085 <https://reviews.llvm.org/D126085>, but was split out as we didn't have a good example of such a transform.  As can be seen in the test diffs, we have the recently added concat_vector(loads) -> strided_load transform (from D147713 <https://reviews.llvm.org/D147713>) which now benefits from the unaligned support.

While making this change, I realized that we actually *do* support unaligned vector loads and stores of all types via conversion to i8 element type.  For contiguous loads and stores, we actually already implement this in the backend - though we don't tell the optimizer that.  For indexed, lowering to i8 requires complicated addressing.  For indexed and segmented, we'd have to use indexed.  All around, doesn't seem worthwhile pursuing, but makes for an interesting observation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149375

Files:
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
  llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

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