[llvm] 0b5396b - [LegalizeVectorOps] Use all ones mask when expanding i1 VP_SELECT.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-04-27T08:26:16-07:00
New Revision: 0b5396b163b6ba014679a6af365747303b95cf97

URL: https://github.com/llvm/llvm-project/commit/0b5396b163b6ba014679a6af365747303b95cf97
DIFF: https://github.com/llvm/llvm-project/commit/0b5396b163b6ba014679a6af365747303b95cf97.diff

LOG: [LegalizeVectorOps] Use all ones mask when expanding i1 VP_SELECT.

We were previously using the condition as the mask. By the semantics
of VP operations, that means that anywhere the condition is false
returns poison and not the false operand.

Use an all ones mask instead.

No tests are affected because RISC-V drops the mask when lowering.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D149310

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index e245b3cb4c6d..18c5fc62b9bf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1304,11 +1304,11 @@ SDValue VectorLegalizer::ExpandVP_SELECT(SDNode *Node) {
     return DAG.UnrollVectorOp(Node);
 
   SDValue Ones = DAG.getAllOnesConstant(DL, VT);
-  SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Mask, EVL);
+  SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Ones, EVL);
 
-  Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Mask, EVL);
-  Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Mask, EVL);
-  return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Mask, EVL);
+  Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Ones, EVL);
+  Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Ones, EVL);
+  return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Ones, EVL);
 }
 
 SDValue VectorLegalizer::ExpandVP_MERGE(SDNode *Node) {