[llvm] 044f27f - [AArch64] Precommit tests for VECTOR_SHUFFLE
Jingu Kang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 27 06:44:53 PDT 2023
Author: Jingu Kang
Date: 2023-04-27T14:44:09+01:00
New Revision: 044f27f62fa5c771385fdac34150307d652e60d6
URL: https://github.com/llvm/llvm-project/commit/044f27f62fa5c771385fdac34150307d652e60d6
DIFF: https://github.com/llvm/llvm-project/commit/044f27f62fa5c771385fdac34150307d652e60d6.diff
LOG: [AArch64] Precommit tests for VECTOR_SHUFFLE
Added:
Modified:
llvm/test/CodeGen/AArch64/shuffles.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/shuffles.ll b/llvm/test/CodeGen/AArch64/shuffles.ll
index e5740fd33b1e..9b908dc0be0a 100644
--- a/llvm/test/CodeGen/AArch64/shuffles.ll
+++ b/llvm/test/CodeGen/AArch64/shuffles.ll
@@ -127,3 +127,138 @@ define <4 x i32> @test0067(<4 x i32> %a, <4 x i32> %b)
%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 7>
ret <4 x i32> %r
}
+
+define <4 x i32> @test_shuf6(<4 x i32> %a, <4 x i32> %b)
+; CHECK-LABEL: test_shuf6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.s[2], v1.s[3]
+; CHECK-NEXT: trn1 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 7, i32 7>
+ ret <4 x i32> %r
+}
+
+define <4 x i16> @test_shuf7(<4 x i16> %a, <4 x i16> %b)
+; CHECK-LABEL: test_shuf7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.h[2], v1.h[3]
+; CHECK-NEXT: trn1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 0, i32 7, i32 7>
+ ret <4 x i16> %r
+}
+
+define <8 x i8> @test_shuf8(<8 x i8> %a, <8 x i8> %b)
+; CHECK-LABEL: test_shuf8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI12_0
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI12_0]
+; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i8> %r
+}
+
+define <8 x i16> @test_shuf9(<8 x i16> %a, <8 x i16> %b)
+; CHECK-LABEL: test_shuf9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI13_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_shuf10(<16 x i8> %a, <16 x i8> %b)
+; CHECK-LABEL: test_shuf10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI14_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8 >
+ ret <16 x i8> %r
+}
+
+define <8 x half> @test_shuf11(<8 x half> %a, <8 x half> %b)
+; CHECK-LABEL: test_shuf11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI15_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x half> %r
+}
+
+define <8 x half> @test_shuf12(<8 x half> %a, <8 x half> %b)
+; CHECK-LABEL: test_shuf12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI16_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 1, i32 15>
+ ret <8 x half> %r
+}
+
+define <8 x half> @test_shuf13(<8 x half> %a, <8 x half> %b)
+; CHECK-LABEL: test_shuf13:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI17_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 2, i32 0, i32 0, i32 0, i32 8, i32 1, i32 15>
+ ret <8 x half> %r
+}
+
+define <8 x half> @test_shuf14(<8 x half> %a, <8 x half> %b)
+; CHECK-LABEL: test_shuf14:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI18_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 2, i32 1, i32 1, i32 0, i32 8, i32 1, i32 15>
+ ret <8 x half> %r
+}
+
+define <8 x half> @test_shuf15(<8 x half> %a, <8 x half> %b)
+; CHECK-LABEL: test_shuf15:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI19_0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_0]
+; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-NEXT: ret
+{
+ %r = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 2, i32 7, i32 2, i32 0, i32 3, i32 2, i32 15>
+ ret <8 x half> %r
+}
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