[llvm] fb1ecab - [HWASAN] Fix X86 ClInstrumentWithCalls
Vitaly Buka via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 26 23:30:17 PDT 2023
Author: Vitaly Buka
Date: 2023-04-26T23:30:01-07:00
New Revision: fb1ecab02328fa2d9ebd4d91aa27a7b1e685a9c8
URL: https://github.com/llvm/llvm-project/commit/fb1ecab02328fa2d9ebd4d91aa27a7b1e685a9c8
DIFF: https://github.com/llvm/llvm-project/commit/fb1ecab02328fa2d9ebd4d91aa27a7b1e685a9c8.diff
LOG: [HWASAN] Fix X86 ClInstrumentWithCalls
It was always ON for X86.
Added:
Modified:
llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index e6e570ebb330..500141953504 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -239,7 +239,9 @@ bool shouldInstrumentStack(const Triple &TargetTriple) {
}
bool shouldInstrumentWithCalls(const Triple &TargetTriple) {
- return ClInstrumentWithCalls || TargetTriple.getArch() == Triple::x86_64;
+ return ClInstrumentWithCalls.getNumOccurrences()
+ ? ClInstrumentWithCalls
+ : TargetTriple.getArch() == Triple::x86_64;
}
bool mightUseStackSafetyAnalysis(bool DisableOptimization) {
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
index 20a3242de5fa..a07d242a6780 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
@@ -37,25 +37,48 @@ define void @test_alloca() sanitize_hwaddress {
; INLINE-LABEL: define void @test_alloca
; INLINE-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; INLINE-NEXT: entry:
-; INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; INLINE-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
-; INLINE-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
-; INLINE-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
-; INLINE-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
-; INLINE-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63
-; INLINE-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 57
-; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP4]], 63
+; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
+; INLINE-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
+; INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
+; INLINE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44
+; INLINE-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP5]]
+; INLINE-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
+; INLINE-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8
+; INLINE-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56
+; INLINE-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12
+; INLINE-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1
+; INLINE-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8
+; INLINE-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]]
+; INLINE-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8
+; INLINE-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295
+; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1
+; INLINE-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; INLINE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP4]], 57
+; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP15]], 63
; INLINE-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
-; INLINE-NEXT: [[TMP5:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
-; INLINE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X]] to i64
-; INLINE-NEXT: [[TMP7:%.*]] = shl i64 [[TMP5]], 57
-; INLINE-NEXT: [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]]
-; INLINE-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; INLINE-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP5]] to i8
-; INLINE-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP9]], i64 16)
+; INLINE-NEXT: [[TMP16:%.*]] = xor i64 [[TMP2]], 0
+; INLINE-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64
+; INLINE-NEXT: [[TMP18:%.*]] = shl i64 [[TMP16]], 57
+; INLINE-NEXT: [[TMP19:%.*]] = or i64 [[TMP17]], [[TMP18]]
+; INLINE-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr
+; INLINE-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP16]] to i8
+; INLINE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[X]] to i64
+; INLINE-NEXT: [[TMP22:%.*]] = and i64 [[TMP21]], 144115188075855871
+; INLINE-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 4
+; INLINE-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP23]]
+; INLINE-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP24]], i32 0
+; INLINE-NEXT: store i8 4, ptr [[TMP25]], align 1
+; INLINE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[X]], i32 15
+; INLINE-NEXT: store i8 [[TMP20]], ptr [[TMP26]], align 1
; INLINE-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
-; INLINE-NEXT: [[TMP10:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
-; INLINE-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP10]], i64 16)
+; INLINE-NEXT: [[TMP27:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
+; INLINE-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[X]] to i64
+; INLINE-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 144115188075855871
+; INLINE-NEXT: [[TMP30:%.*]] = lshr i64 [[TMP29]], 4
+; INLINE-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP30]]
+; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP31]], i8 [[TMP27]], i64 1, i1 false)
; INLINE-NEXT: ret void
;
entry:
@@ -95,27 +118,78 @@ define i32 @test_simple(ptr %a) sanitize_hwaddress {
; INLINE-LABEL: define i32 @test_simple
; INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0]] personality ptr @__hwasan_personality_thunk {
; INLINE-NEXT: entry:
-; INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; INLINE-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
-; INLINE-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
-; INLINE-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
-; INLINE-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
-; INLINE-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63
-; INLINE-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 57
-; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP4]], 63
+; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
+; INLINE-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
+; INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
+; INLINE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44
+; INLINE-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_simple to i64), [[TMP5]]
+; INLINE-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
+; INLINE-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8
+; INLINE-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56
+; INLINE-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12
+; INLINE-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1
+; INLINE-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8
+; INLINE-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]]
+; INLINE-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8
+; INLINE-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295
+; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1
+; INLINE-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; INLINE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP4]], 57
+; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP15]], 63
; INLINE-NEXT: [[BUF_SROA_0:%.*]] = alloca { i8, [15 x i8] }, align 16
-; INLINE-NEXT: [[TMP5:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
-; INLINE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
-; INLINE-NEXT: [[TMP7:%.*]] = shl i64 [[TMP5]], 57
-; INLINE-NEXT: [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]]
-; INLINE-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; INLINE-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP5]] to i8
-; INLINE-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[TMP9]], i64 16)
-; INLINE-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64
-; INLINE-NEXT: call void @__hwasan_store1(i64 [[TMP10]])
+; INLINE-NEXT: [[TMP16:%.*]] = xor i64 [[TMP2]], 0
+; INLINE-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
+; INLINE-NEXT: [[TMP18:%.*]] = shl i64 [[TMP16]], 57
+; INLINE-NEXT: [[TMP19:%.*]] = or i64 [[TMP17]], [[TMP18]]
+; INLINE-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr
+; INLINE-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP16]] to i8
+; INLINE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
+; INLINE-NEXT: [[TMP22:%.*]] = and i64 [[TMP21]], 144115188075855871
+; INLINE-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 4
+; INLINE-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP23]]
+; INLINE-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP24]], i32 0
+; INLINE-NEXT: store i8 1, ptr [[TMP25]], align 1
+; INLINE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BUF_SROA_0]], i32 15
+; INLINE-NEXT: store i8 [[TMP20]], ptr [[TMP26]], align 1
+; INLINE-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64
+; INLINE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 57
+; INLINE-NEXT: [[TMP29:%.*]] = trunc i64 [[TMP28]] to i8
+; INLINE-NEXT: [[TMP30:%.*]] = and i64 [[TMP27]], 144115188075855871
+; INLINE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4
+; INLINE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP31]]
+; INLINE-NEXT: [[TMP33:%.*]] = load i8, ptr [[TMP32]], align 1
+; INLINE-NEXT: [[TMP34:%.*]] = icmp ne i8 [[TMP29]], [[TMP33]]
+; INLINE-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP49:%.*]], !prof [[PROF1:![0-9]+]]
+; INLINE: 35:
+; INLINE-NEXT: [[TMP36:%.*]] = icmp ugt i8 [[TMP33]], 15
+; INLINE-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP38:%.*]], !prof [[PROF1]]
+; INLINE: 37:
+; INLINE-NEXT: call void asm sideeffect "int3\0Anopl 80([[RAX:%.*]])", "{rdi}"(i64 [[TMP27]])
+; INLINE-NEXT: unreachable
+; INLINE: 38:
+; INLINE-NEXT: [[TMP39:%.*]] = and i64 [[TMP27]], 15
+; INLINE-NEXT: [[TMP40:%.*]] = trunc i64 [[TMP39]] to i8
+; INLINE-NEXT: [[TMP41:%.*]] = add i8 [[TMP40]], 0
+; INLINE-NEXT: [[TMP42:%.*]] = icmp uge i8 [[TMP41]], [[TMP33]]
+; INLINE-NEXT: br i1 [[TMP42]], label [[TMP37]], label [[TMP43:%.*]], !prof [[PROF1]]
+; INLINE: 43:
+; INLINE-NEXT: [[TMP44:%.*]] = or i64 [[TMP30]], 15
+; INLINE-NEXT: [[TMP45:%.*]] = inttoptr i64 [[TMP44]] to ptr
+; INLINE-NEXT: [[TMP46:%.*]] = load i8, ptr [[TMP45]], align 1
+; INLINE-NEXT: [[TMP47:%.*]] = icmp ne i8 [[TMP29]], [[TMP46]]
+; INLINE-NEXT: br i1 [[TMP47]], label [[TMP37]], label [[TMP48:%.*]], !prof [[PROF1]]
+; INLINE: 48:
+; INLINE-NEXT: br label [[TMP49]]
+; INLINE: 49:
; INLINE-NEXT: store volatile i8 0, ptr [[BUF_SROA_0_HWASAN]], align 4
-; INLINE-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
-; INLINE-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[TMP11]], i64 16)
+; INLINE-NEXT: [[TMP50:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
+; INLINE-NEXT: [[TMP51:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
+; INLINE-NEXT: [[TMP52:%.*]] = and i64 [[TMP51]], 144115188075855871
+; INLINE-NEXT: [[TMP53:%.*]] = lshr i64 [[TMP52]], 4
+; INLINE-NEXT: [[TMP54:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP53]]
+; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP54]], i8 [[TMP50]], i64 1, i1 false)
; INLINE-NEXT: ret i32 0
;
entry:
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
index 47bd257776e2..559a6fbc30e3 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
@@ -33,18 +33,82 @@ define i8 @test_load8(ptr %a) sanitize_hwaddress {
; ABORT-INLINE-LABEL: define i8 @test_load8
; ABORT-INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; ABORT-INLINE-NEXT: entry:
-; ABORT-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; ABORT-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; ABORT-INLINE-NEXT: call void @__hwasan_load1(i64 [[TMP0]])
+; ABORT-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; ABORT-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; ABORT-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; ABORT-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; ABORT-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; ABORT-INLINE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 57
+; ABORT-INLINE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
+; ABORT-INLINE-NEXT: [[TMP7:%.*]] = and i64 [[TMP4]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 4
+; ABORT-INLINE-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[TMP8]]
+; ABORT-INLINE-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
+; ABORT-INLINE-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP6]], [[TMP10]]
+; ABORT-INLINE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP26:%.*]], !prof [[PROF1:![0-9]+]]
+; ABORT-INLINE: 12:
+; ABORT-INLINE-NEXT: [[TMP13:%.*]] = icmp ugt i8 [[TMP10]], 15
+; ABORT-INLINE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 14:
+; ABORT-INLINE-NEXT: call void asm sideeffect "int3\0Anopl 64([[RAX:%.*]])", "{rdi}"(i64 [[TMP4]])
+; ABORT-INLINE-NEXT: unreachable
+; ABORT-INLINE: 15:
+; ABORT-INLINE-NEXT: [[TMP16:%.*]] = and i64 [[TMP4]], 15
+; ABORT-INLINE-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i8
+; ABORT-INLINE-NEXT: [[TMP18:%.*]] = add i8 [[TMP17]], 0
+; ABORT-INLINE-NEXT: [[TMP19:%.*]] = icmp uge i8 [[TMP18]], [[TMP10]]
+; ABORT-INLINE-NEXT: br i1 [[TMP19]], label [[TMP14]], label [[TMP20:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 20:
+; ABORT-INLINE-NEXT: [[TMP21:%.*]] = or i64 [[TMP7]], 15
+; ABORT-INLINE-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr
+; ABORT-INLINE-NEXT: [[TMP23:%.*]] = load i8, ptr [[TMP22]], align 1
+; ABORT-INLINE-NEXT: [[TMP24:%.*]] = icmp ne i8 [[TMP6]], [[TMP23]]
+; ABORT-INLINE-NEXT: br i1 [[TMP24]], label [[TMP14]], label [[TMP25:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 25:
+; ABORT-INLINE-NEXT: br label [[TMP26]]
+; ABORT-INLINE: 26:
; ABORT-INLINE-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4
; ABORT-INLINE-NEXT: ret i8 [[B]]
;
; RECOVER-INLINE-LABEL: define i8 @test_load8
; RECOVER-INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; RECOVER-INLINE-NEXT: entry:
-; RECOVER-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; RECOVER-INLINE-NEXT: call void @__hwasan_load1_noabort(i64 [[TMP0]])
+; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; RECOVER-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; RECOVER-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; RECOVER-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; RECOVER-INLINE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 57
+; RECOVER-INLINE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
+; RECOVER-INLINE-NEXT: [[TMP7:%.*]] = and i64 [[TMP4]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 4
+; RECOVER-INLINE-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[TMP8]]
+; RECOVER-INLINE-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
+; RECOVER-INLINE-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP6]], [[TMP10]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP26:%.*]], !prof [[PROF1:![0-9]+]]
+; RECOVER-INLINE: 12:
+; RECOVER-INLINE-NEXT: [[TMP13:%.*]] = icmp ugt i8 [[TMP10]], 15
+; RECOVER-INLINE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]
+; RECOVER-INLINE: 14:
+; RECOVER-INLINE-NEXT: call void asm sideeffect "int3\0Anopl 96([[RAX:%.*]])", "{rdi}"(i64 [[TMP4]])
+; RECOVER-INLINE-NEXT: br label [[TMP25:%.*]]
+; RECOVER-INLINE: 15:
+; RECOVER-INLINE-NEXT: [[TMP16:%.*]] = and i64 [[TMP4]], 15
+; RECOVER-INLINE-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i8
+; RECOVER-INLINE-NEXT: [[TMP18:%.*]] = add i8 [[TMP17]], 0
+; RECOVER-INLINE-NEXT: [[TMP19:%.*]] = icmp uge i8 [[TMP18]], [[TMP10]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP19]], label [[TMP14]], label [[TMP20:%.*]], !prof [[PROF1]]
+; RECOVER-INLINE: 20:
+; RECOVER-INLINE-NEXT: [[TMP21:%.*]] = or i64 [[TMP7]], 15
+; RECOVER-INLINE-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP23:%.*]] = load i8, ptr [[TMP22]], align 1
+; RECOVER-INLINE-NEXT: [[TMP24:%.*]] = icmp ne i8 [[TMP6]], [[TMP23]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP24]], label [[TMP14]], label [[TMP25]], !prof [[PROF1]]
+; RECOVER-INLINE: 25:
+; RECOVER-INLINE-NEXT: br label [[TMP26]]
+; RECOVER-INLINE: 26:
; RECOVER-INLINE-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4
; RECOVER-INLINE-NEXT: ret i8 [[B]]
;
@@ -78,18 +142,26 @@ define i40 @test_load40(ptr %a) sanitize_hwaddress {
; ABORT-INLINE-LABEL: define i40 @test_load40
; ABORT-INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0]] {
; ABORT-INLINE-NEXT: entry:
-; ABORT-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; ABORT-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; ABORT-INLINE-NEXT: call void @__hwasan_loadN(i64 [[TMP0]], i64 5)
+; ABORT-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; ABORT-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; ABORT-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; ABORT-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; ABORT-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; ABORT-INLINE-NEXT: call void @__hwasan_loadN(i64 [[TMP4]], i64 5)
; ABORT-INLINE-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4
; ABORT-INLINE-NEXT: ret i40 [[B]]
;
; RECOVER-INLINE-LABEL: define i40 @test_load40
; RECOVER-INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0]] {
; RECOVER-INLINE-NEXT: entry:
-; RECOVER-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; RECOVER-INLINE-NEXT: call void @__hwasan_loadN_noabort(i64 [[TMP0]], i64 5)
+; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; RECOVER-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; RECOVER-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; RECOVER-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; RECOVER-INLINE-NEXT: call void @__hwasan_loadN_noabort(i64 [[TMP4]], i64 5)
; RECOVER-INLINE-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4
; RECOVER-INLINE-NEXT: ret i40 [[B]]
;
@@ -123,18 +195,82 @@ define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress {
; ABORT-INLINE-LABEL: define void @test_store8
; ABORT-INLINE-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] {
; ABORT-INLINE-NEXT: entry:
-; ABORT-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; ABORT-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; ABORT-INLINE-NEXT: call void @__hwasan_store1(i64 [[TMP0]])
+; ABORT-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; ABORT-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; ABORT-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; ABORT-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; ABORT-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; ABORT-INLINE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 57
+; ABORT-INLINE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
+; ABORT-INLINE-NEXT: [[TMP7:%.*]] = and i64 [[TMP4]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 4
+; ABORT-INLINE-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[TMP8]]
+; ABORT-INLINE-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
+; ABORT-INLINE-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP6]], [[TMP10]]
+; ABORT-INLINE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP26:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 12:
+; ABORT-INLINE-NEXT: [[TMP13:%.*]] = icmp ugt i8 [[TMP10]], 15
+; ABORT-INLINE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 14:
+; ABORT-INLINE-NEXT: call void asm sideeffect "int3\0Anopl 80([[RAX:%.*]])", "{rdi}"(i64 [[TMP4]])
+; ABORT-INLINE-NEXT: unreachable
+; ABORT-INLINE: 15:
+; ABORT-INLINE-NEXT: [[TMP16:%.*]] = and i64 [[TMP4]], 15
+; ABORT-INLINE-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i8
+; ABORT-INLINE-NEXT: [[TMP18:%.*]] = add i8 [[TMP17]], 0
+; ABORT-INLINE-NEXT: [[TMP19:%.*]] = icmp uge i8 [[TMP18]], [[TMP10]]
+; ABORT-INLINE-NEXT: br i1 [[TMP19]], label [[TMP14]], label [[TMP20:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 20:
+; ABORT-INLINE-NEXT: [[TMP21:%.*]] = or i64 [[TMP7]], 15
+; ABORT-INLINE-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr
+; ABORT-INLINE-NEXT: [[TMP23:%.*]] = load i8, ptr [[TMP22]], align 1
+; ABORT-INLINE-NEXT: [[TMP24:%.*]] = icmp ne i8 [[TMP6]], [[TMP23]]
+; ABORT-INLINE-NEXT: br i1 [[TMP24]], label [[TMP14]], label [[TMP25:%.*]], !prof [[PROF1]]
+; ABORT-INLINE: 25:
+; ABORT-INLINE-NEXT: br label [[TMP26]]
+; ABORT-INLINE: 26:
; ABORT-INLINE-NEXT: store i8 [[B]], ptr [[A]], align 4
; ABORT-INLINE-NEXT: ret void
;
; RECOVER-INLINE-LABEL: define void @test_store8
; RECOVER-INLINE-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-INLINE-NEXT: entry:
-; RECOVER-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; RECOVER-INLINE-NEXT: call void @__hwasan_store1_noabort(i64 [[TMP0]])
+; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; RECOVER-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; RECOVER-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; RECOVER-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; RECOVER-INLINE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 57
+; RECOVER-INLINE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
+; RECOVER-INLINE-NEXT: [[TMP7:%.*]] = and i64 [[TMP4]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 4
+; RECOVER-INLINE-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[TMP8]]
+; RECOVER-INLINE-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
+; RECOVER-INLINE-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP6]], [[TMP10]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP26:%.*]], !prof [[PROF1]]
+; RECOVER-INLINE: 12:
+; RECOVER-INLINE-NEXT: [[TMP13:%.*]] = icmp ugt i8 [[TMP10]], 15
+; RECOVER-INLINE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]
+; RECOVER-INLINE: 14:
+; RECOVER-INLINE-NEXT: call void asm sideeffect "int3\0Anopl 112([[RAX:%.*]])", "{rdi}"(i64 [[TMP4]])
+; RECOVER-INLINE-NEXT: br label [[TMP25:%.*]]
+; RECOVER-INLINE: 15:
+; RECOVER-INLINE-NEXT: [[TMP16:%.*]] = and i64 [[TMP4]], 15
+; RECOVER-INLINE-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i8
+; RECOVER-INLINE-NEXT: [[TMP18:%.*]] = add i8 [[TMP17]], 0
+; RECOVER-INLINE-NEXT: [[TMP19:%.*]] = icmp uge i8 [[TMP18]], [[TMP10]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP19]], label [[TMP14]], label [[TMP20:%.*]], !prof [[PROF1]]
+; RECOVER-INLINE: 20:
+; RECOVER-INLINE-NEXT: [[TMP21:%.*]] = or i64 [[TMP7]], 15
+; RECOVER-INLINE-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP23:%.*]] = load i8, ptr [[TMP22]], align 1
+; RECOVER-INLINE-NEXT: [[TMP24:%.*]] = icmp ne i8 [[TMP6]], [[TMP23]]
+; RECOVER-INLINE-NEXT: br i1 [[TMP24]], label [[TMP14]], label [[TMP25]], !prof [[PROF1]]
+; RECOVER-INLINE: 25:
+; RECOVER-INLINE-NEXT: br label [[TMP26]]
+; RECOVER-INLINE: 26:
; RECOVER-INLINE-NEXT: store i8 [[B]], ptr [[A]], align 4
; RECOVER-INLINE-NEXT: ret void
;
@@ -168,18 +304,26 @@ define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress {
; ABORT-INLINE-LABEL: define void @test_store40
; ABORT-INLINE-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] {
; ABORT-INLINE-NEXT: entry:
-; ABORT-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; ABORT-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; ABORT-INLINE-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 5)
+; ABORT-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; ABORT-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; ABORT-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; ABORT-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; ABORT-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; ABORT-INLINE-NEXT: call void @__hwasan_storeN(i64 [[TMP4]], i64 5)
; ABORT-INLINE-NEXT: store i40 [[B]], ptr [[A]], align 4
; ABORT-INLINE-NEXT: ret void
;
; RECOVER-INLINE-LABEL: define void @test_store40
; RECOVER-INLINE-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-INLINE-NEXT: entry:
-; RECOVER-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; RECOVER-INLINE-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP0]], i64 5)
+; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; RECOVER-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; RECOVER-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; RECOVER-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; RECOVER-INLINE-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP4]], i64 5)
; RECOVER-INLINE-NEXT: store i40 [[B]], ptr [[A]], align 4
; RECOVER-INLINE-NEXT: ret void
;
@@ -213,18 +357,26 @@ define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress {
; ABORT-INLINE-LABEL: define void @test_store_unaligned
; ABORT-INLINE-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
; ABORT-INLINE-NEXT: entry:
-; ABORT-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; ABORT-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; ABORT-INLINE-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 8)
+; ABORT-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; ABORT-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; ABORT-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; ABORT-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; ABORT-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; ABORT-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; ABORT-INLINE-NEXT: call void @__hwasan_storeN(i64 [[TMP4]], i64 8)
; ABORT-INLINE-NEXT: store i64 [[B]], ptr [[A]], align 4
; ABORT-INLINE-NEXT: ret void
;
; RECOVER-INLINE-LABEL: define void @test_store_unaligned
; RECOVER-INLINE-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-INLINE-NEXT: entry:
-; RECOVER-INLINE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
-; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
-; RECOVER-INLINE-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP0]], i64 8)
+; RECOVER-INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
+; RECOVER-INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855871
+; RECOVER-INLINE-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
+; RECOVER-INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
+; RECOVER-INLINE-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
+; RECOVER-INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; RECOVER-INLINE-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP4]], i64 8)
; RECOVER-INLINE-NEXT: store i64 [[B]], ptr [[A]], align 4
; RECOVER-INLINE-NEXT: ret void
;
More information about the llvm-commits
mailing list