[PATCH] D141473: [PowerPC] Simplify fp-to-int store optimization

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf marked 2 inline comments as done.
qiucf added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrP10.td:1258
+  def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
+            (PSTXSDpc (COPY_TO_REGCLASS $src, VSRC), $dst, 0)>;
 
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shchenz wrote:
> Can you explain why we need to copy to regclass `VSRC`? The definition of `PSTXSDpc` seems requiring RC to be `VFRC` for `$src`.
Thanks, I updated the copied classes to respective regclass of the instructions. This `COPY_TO_REGCLASS` is needed, otherewise we'll get a `HW typeset is empty` build failure.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3161
+def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8),
+          (STXSDX (COPY_TO_REGCLASS $src, VSRC), ForceXForm:$dst)>;
 
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shchenz wrote:
> Compared with the lines at 4046, we seems missing some pattern here? This is for `[HasVSX, NoP9Vector]`.
This is for pwr7/pwr8 only, other patterns are located at `HasP8Vector` `HasVSX` section, so that they can be shared with pwr9.


Repository:
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  https://reviews.llvm.org/D141473/new/

https://reviews.llvm.org/D141473