[llvm] 5854b39 - [RISCV] Remove the uret instruction.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 26 17:15:12 PDT 2023
Author: Craig Topper
Date: 2023-04-26T17:11:58-07:00
New Revision: 5854b39847251fded061b46ba03df6a361deadf8
URL: https://github.com/llvm/llvm-project/commit/5854b39847251fded061b46ba03df6a361deadf8
DIFF: https://github.com/llvm/llvm-project/commit/5854b39847251fded061b46ba03df6a361deadf8.diff
LOG: [RISCV] Remove the uret instruction.
This was part of the N extension which did not make it into
version 1.12 of the privilege specification.
Reviewed By: jrtc27
Differential Revision: https://reviews.llvm.org/D149308
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/interrupt-attr.ll
llvm/test/MC/RISCV/priv-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1dcc1bfd43bda..8104f19b0f474 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14531,9 +14531,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
StringRef Kind =
MF.getFunction().getFnAttribute("interrupt").getValueAsString();
- if (Kind == "user")
- RetOpc = RISCVISD::URET_GLUE;
- else if (Kind == "supervisor")
+ if (Kind == "supervisor")
RetOpc = RISCVISD::SRET_GLUE;
else
RetOpc = RISCVISD::MRET_GLUE;
@@ -14607,7 +14605,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
case RISCVISD::FIRST_NUMBER:
break;
NODE_NAME_CASE(RET_GLUE)
- NODE_NAME_CASE(URET_GLUE)
NODE_NAME_CASE(SRET_GLUE)
NODE_NAME_CASE(MRET_GLUE)
NODE_NAME_CASE(CALL)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index ddfe319efea90..b48cdb2f08211 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -28,7 +28,6 @@ namespace RISCVISD {
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
RET_GLUE,
- URET_GLUE,
SRET_GLUE,
MRET_GLUE,
CALL,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b125ed5e8352a..5e1131a957a70 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -57,8 +57,6 @@ def riscv_call : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
SDNPVariadic]>;
def riscv_ret_glue : SDNode<"RISCVISD::RET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-def riscv_uret_glue : SDNode<"RISCVISD::URET_GLUE", SDTNone,
- [SDNPHasChain, SDNPOptInGlue]>;
def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
@@ -822,12 +820,6 @@ def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
//===----------------------------------------------------------------------===//
let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
-def URET : Priv<"uret", 0b0000000>, Sched<[]> {
- let rd = 0;
- let rs1 = 0;
- let rs2 = 0b00010;
-}
-
def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
let rd = 0;
let rs1 = 0;
@@ -1562,7 +1554,6 @@ def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []>,
def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
-def : Pat<(riscv_uret_glue), (URET X0, X0)>;
def : Pat<(riscv_sret_glue), (SRET X0, X0)>;
def : Pat<(riscv_mret_glue), (MRET X0, X0)>;
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr.ll b/llvm/test/CodeGen/RISCV/interrupt-attr.ll
index 2eb8dbe74453f..eb683f01704f1 100644
--- a/llvm/test/CodeGen/RISCV/interrupt-attr.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr.ll
@@ -14,23 +14,16 @@
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
;
-; Checking for special return instructions (uret, sret, mret).
+; Checking for special return instructions (sret, mret).
;
-define void @foo_user() #0 {
-; CHECK-LABEL: foo_user:
-; CHECK: # %bb.0:
-; CHECK-NEXT: uret
- ret void
-}
-
-define void @foo_supervisor() #1 {
+define void @foo_supervisor() #0 {
; CHECK-LABEL: foo_supervisor:
; CHECK: # %bb.0:
; CHECK-NEXT: sret
ret void
}
-define void @foo_machine() #2 {
+define void @foo_machine() #1 {
; CHECK-LABEL: foo_machine:
; CHECK: # %bb.0:
; CHECK-NEXT: mret
@@ -49,7 +42,7 @@ define void @foo_machine() #2 {
;
declare i32 @otherfoo(...)
-define void @foo_with_call() #2 {
+define void @foo_with_call() #1 {
;
; CHECK-RV32-LABEL: foo_with_call:
; CHECK-RV32: # %bb.0:
@@ -547,7 +540,7 @@ define void @foo_with_call() #2 {
;
; Additionally check frame pointer and return address are properly saved.
;
-define void @foo_fp_with_call() #3 {
+define void @foo_fp_with_call() #2 {
;
; CHECK-RV32-LABEL: foo_fp_with_call:
; CHECK-RV32: # %bb.0:
@@ -1060,7 +1053,6 @@ define void @foo_fp_with_call() #3 {
ret void
}
-attributes #0 = { nounwind "interrupt"="user" }
-attributes #1 = { nounwind "interrupt"="supervisor" }
-attributes #2 = { nounwind "interrupt"="machine" }
-attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" }
+attributes #0 = { nounwind "interrupt"="supervisor" }
+attributes #1 = { nounwind "interrupt"="machine" }
+attributes #2 = { nounwind "interrupt"="machine" "frame-pointer"="all" }
diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
index 323acc500d383..561c76bf4fa29 100644
--- a/llvm/test/MC/RISCV/priv-valid.s
+++ b/llvm/test/MC/RISCV/priv-valid.s
@@ -9,10 +9,6 @@
# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: uret
-# CHECK: encoding: [0x73,0x00,0x20,0x00]
-uret
-
# CHECK-INST: sret
# CHECK: encoding: [0x73,0x00,0x20,0x10]
sret
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