[PATCH] D148834: [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 26 14:58:59 PDT 2023


reames updated this revision to Diff 517341.
reames added a comment.

Address review comment


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148834/new/

https://reviews.llvm.org/D148834

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
  llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

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