[PATCH] D148841: [LV] Use SCEV for uniformity analysis across VF
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 26 12:51:51 PDT 2023
fhahn marked 2 inline comments as done.
fhahn added inline comments.
================
Comment at: llvm/lib/Analysis/LoopAccessAnalysis.cpp:2600-2602
+ return SE.getUDivExpr(
+ SCEVRewriteVisitor<SCEVAddRecRewriter>::visit(S->getOperand(0)),
+ SCEVRewriteVisitor<SCEVAddRecRewriter>::visit(S->getOperand(1)));
----------------
nikic wrote:
> Maybe?
Yep that's more compact, thanks!
================
Comment at: llvm/lib/Analysis/LoopAccessAnalysis.cpp:2663
+ IthLaneRewriter.canAnalyze() &&
+ SE->isKnownPredicate(CmpInst::ICMP_EQ, FirstLaneExpr, IthLaneExpr) &&
+ "first and last lane are equal, but not all lanes in between");
----------------
nikic wrote:
> In line with the other comparison?
Updated! Originally the other check was also using `SE->isKnownPredicate` but it was increasing compile-time while not being needed for the first set of motivating cases.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D148841/new/
https://reviews.llvm.org/D148841
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