[PATCH] D148824: AMDGPU: Define sub-class of SGPR_64 for tail call return

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:830
+def Gfx_CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32,
+                                (add (trunc (shl SGPR_64, 15), 1), // s[30:31]
+                                     (trunc (shl SGPR_64, 18), 14))> { // s[36:37]-s[s62:63]
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cfang wrote:
> sebastian-ne wrote:
> > cdevadas wrote:
> > > @sebastian-ne can you review this part, the gfx scratch SGPRs?
> > > 
> > > The rest of the patch LGTM.
> > Thanks for the fix!
> > 
> > The `s[36:37]-s[s62:63]` range looks good. Why is `s[30:31]` part of `Gfx_CCR_SGPR_64` when it is not part of `CCR_SGPR_64`?
> Actually I just try to recover what were defined before. My understanding is that s[30:31] is still CSR and we want to avoid CSR completely.  I am not sure about  Gfx_CCR_SGPR_64.
> 
> Matt and CD, can you confirm that s[30:31] should not be used as the return address of tail call?  
I think for the compute side we should not use S[30:31] for tail call target addresses as they are now CSRs, and their spills/restores at prolog/epilog are needed for the debug unwinding info. 

def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, **16**))

Here S[30:31] pair is currently part of CCR_SGPR_64. The immediate operand in trunc should be 15 instead of 16 to exclude it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148824/new/

https://reviews.llvm.org/D148824