[llvm] 236898f - [RISCV] Accept zicntr and zihpm command line options
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 26 10:13:19 PDT 2023
Author: Craig Topper
Date: 2023-04-26T10:11:07-07:00
New Revision: 236898f6191af51fd5bd52e62987a1edb58b279b
URL: https://github.com/llvm/llvm-project/commit/236898f6191af51fd5bd52e62987a1edb58b279b
DIFF: https://github.com/llvm/llvm-project/commit/236898f6191af51fd5bd52e62987a1edb58b279b.diff
LOG: [RISCV] Accept zicntr and zihpm command line options
This change adds the definition of the two extensions, but does not either a) make any register definitions conditional on them or b) enabled the extensions by default.
This is somewhat analogous to https://reviews.llvm.org/D143953, but with some key differences. The best discussion I can find on status is here: https://github.com/riscv/riscv-profiles/issues/43. These were removed between document version 2.1 and 2.2, but were not defined as new extensions in 2.2. That addition came later - in March 2022.
According to https://drive.google.com/file/d/1qa57pePesOiDOrNzxuuGFhCL4Rbi9AYB/view these were ratified in March 2023.
Reviewed By: asb, reames
Differential Revision: https://reviews.llvm.org/D144215
Added:
Modified:
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
################################################################################
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index daec01d5bd2c..b7f26bddea44 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -109,9 +109,11 @@ on support follow.
``Zicbom`` Assembly Support
``Zicbop`` Assembly Support
``Zicboz`` Assembly Support
+ ``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
``Zihintpause`` Assembly Support
+ ``Zihpm`` (`See Note <#riscv-i2p1-note>`__)
``Zkn`` Supported
``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__)
``Zkne`` Supported (`See note <#riscv-scalar-crypto-note2>`__)
@@ -165,8 +167,8 @@ Supported
.. _riscv-i2p1-note:
-``zicsr``, ``zifencei``
- Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions, but were no longer required by the base ISA. This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document. LLVM currently implements version 2.1 of the base specification. To maintain compatibility, instructions from these extensions are accepted without being in the ``-march`` string. LLVM also allows the explicit specification of the extensions in an ``-march`` string.
+``zicntr``, ``zicsr``, ``zifencei``, ``zihpm``
+ Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions, but were no longer required by the base ISA. This change is partially described in "Preface to Document Version 20190608-Base-Ratified" from the specification document (the ``zicntr`` and ``zihpm`` bits are not mentioned). LLVM currently implements version 2.1 of the base specification. To maintain compatibility, instructions from these extensions are accepted without being in the ``-march`` string. LLVM also allows the explicit specification of the extensions in an ``-march`` string.
Experimental Extensions
=======================
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 42fc2d322214..482811e8c200 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -107,8 +107,10 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
+ {"zicntr", RISCVExtensionVersion{1, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
+ {"zihpm", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index cc17184ba016..5bf634e87fc3 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,14 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZicntr
+ : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
+ "'zicntr' (Base Counters and Timers)">;
+
+def FeatureStdExtZihpm
+ : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
+ "'zihpm' (Hardware Performance Counters)">;
+
def FeatureStdExtZfhmin
: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 5ddfad5eddb9..19a19c847ab2 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -54,6 +54,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
@@ -130,6 +132,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
@@ -201,6 +205,8 @@
; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
+; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0"
+; RV32ZIHPM: .attribute 5, "rv32i2p1_zihpm1p0"
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
@@ -276,6 +282,8 @@
; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
+; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0"
+; RV64ZIHPM: .attribute 5, "rv64i2p1_zihpm1p0"
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
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