[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via llvm-commits]

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This implements the v0.1 draft extension.

amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must be even registers. I've opted to implement this restriction in RISCVAsmParser::validateInstruction even though for codegen we'll need a new register class and can then remove this validation. My reasoning is that this validation is easy to implement and review, while ensuring the register class is correct as described isn't so easy without testing that is only added when codegen is implemented. Admittedly, the need to check for the aq/rl/aqrl opcode variants makes the validateInstruction
logic a bit uglier. Happy to switch approach if preferred by reviewers.

It's not a pre-requisite for this patch, but we likely want to have an asm constraint for even registers. I've filed an issue here https://github.com/riscv-non-isa/riscv-c-api-doc/issues/37


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149248

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

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