[PATCH] D149068: [llvm-mca][RISCV] Fix checking if data valid in createInstrument

Tue Apr 25 19:38:33 PDT 2023

andreadb accepted this revision.
andreadb added a comment.

In D149068#4296291 <https://reviews.llvm.org/D149068#4296291>, @craig.topper wrote:

> In D149068#4294263 <https://reviews.llvm.org/D149068#4294263>, @andreadb wrote:
>
>> In D149068#4292725 <https://reviews.llvm.org/D149068#4292725>, @michaelmaitland wrote:
>>
>>>> Though I'm a little surprised it doesn't print a warning or even error for invalid instruments. Is there any reason behind this?
>>>
>>> Debug warning is printed on line 85 of `RISCVCustomBehaviour.cpp`. We print an actual error and exit from MCA here <https://github.com/llvm/llvm-project/blob/53791896de3fcc5606c190fa4e4552383ee1dcb8/llvm/tools/llvm-mca/CodeRegionGenerator.cpp#L190>
>>
>> It would be better if all this custom behaviour logic was properly tested. If I remember it correctly, the plan was to contribute a generic scheduling model as a follow-up to test all of this. Is that still a plan?
>
> It's not clear how to define a "generic" scheduling model. An in order CPU and an out of order CPU might have very different implementations for the RISC-V vector extension. Creating "generic" scheduler starts becoming equivalent to architecting a CPU.
>
> We're hoping to upstream a scheduler based on a real hardware implementation soon.

Sounds good. Thanks for the info.

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