[PATCH] D149181: [RISCV] Remove one use restriction the scalar from combineBinOpToReduce.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 25 13:03:50 PDT 2023
craig.topper created this revision.
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If multiple reductions use the neutral start value, this prevented
us from optimizing any of them.
This increases the number of scalar->vector operations but reduces
the number of scalar operations.
Note, we were already inconsistent about the one use check when we
peeked through INSERT_SUBVECTORs.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149181
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
Index: llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
+++ llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
@@ -282,13 +282,12 @@
; CHECK-LABEL: reduce_fadd4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v10, zero
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: vfmv.s.f v8, fa1
+; CHECK-NEXT: vfredusum.vs v8, v9, v8
; CHECK-NEXT: vfmv.f.s fa4, v8
-; CHECK-NEXT: fadd.s fa5, fa5, fa0
-; CHECK-NEXT: fadd.s fa4, fa4, fa1
; CHECK-NEXT: fdiv.s fa0, fa5, fa4
; CHECK-NEXT: ret
entry:
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9167,9 +9167,6 @@
0))
return SDValue();
- if (!ScalarV.hasOneUse())
- return SDValue();
-
SDValue NewStart = N->getOperand(1 - ReduceIdx);
SDLoc DL(N);
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