[PATCH] D148096: [AMDGPU][GlobalISel] Widen the vector operand in G_BUILD/INSERT/EXTRACT_VECTOR

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:135
+// Increase the number of vector elements to reach the next legal RegClass.
+static LegalizeMutation moreElementsToNextExistingRegClass(unsigned TypeIdx) {
+  return [=](const LegalityQuery &Query) {
----------------
Can we assert that the element type is s32 or s64? (Do the current rules ensure that?)

Can we assert that the type size is < MaxRegisterSize? Falling off the end of the "for" loop should really be unreachable.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:237
 
+static LegalityPredicate isNotAnExistingRegClassType(unsigned TypeIdx) {
+  return [=](const LegalityQuery &Query) {
----------------
Do we really need this new concept of "RegClassType" in addition to "RegisterType"? I'd really prefer if we can make them the same thing.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148096/new/

https://reviews.llvm.org/D148096