[llvm] 85aa172 - [LoopReroll] Regenerate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 25 03:57:44 PDT 2023
Author: Nikita Popov
Date: 2023-04-25T12:57:05+02:00
New Revision: 85aa1728ac64194c672eaabb0466934cc68788b6
URL: https://github.com/llvm/llvm-project/commit/85aa1728ac64194c672eaabb0466934cc68788b6
DIFF: https://github.com/llvm/llvm-project/commit/85aa1728ac64194c672eaabb0466934cc68788b6.diff
LOG: [LoopReroll] Regenerate test checks (NFC)
Added:
Modified:
llvm/test/Transforms/LoopReroll/basic.ll
llvm/test/Transforms/LoopReroll/extra_instr.ll
llvm/test/Transforms/LoopReroll/ptrindvar.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopReroll/basic.ll b/llvm/test/Transforms/LoopReroll/basic.ll
index 9143604a50d0c..13fb1236b2634 100644
--- a/llvm/test/Transforms/LoopReroll/basic.ll
+++ b/llvm/test/Transforms/LoopReroll/basic.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -opaque-pointers=0 < %s -passes=loop-reroll -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@@ -11,8 +12,20 @@ target triple = "x86_64-unknown-linux-gnu"
; }
; }
-; Function Attrs: nounwind uwtable
define void @bar(i32* nocapture readnone %x) #0 {
+; CHECK-LABEL: define void @bar
+; CHECK-SAME: (i32* nocapture readnone [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 [[INDVAR]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i32 [[INDVAR]], 500
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -27,17 +40,6 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp sge i32 %add3, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @bar
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %call = tail call i32 @foo(i32 %indvar) #1
-; CHECK: %indvar.next = add i32 %indvar, 1
-; CHECK: %exitcond1 = icmp eq i32 %indvar, 500
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
-
-; CHECK: ret
-
for.end: ; preds = %for.body
ret void
}
@@ -54,6 +56,22 @@ declare i32 @foo(i32)
; Function Attrs: nounwind uwtable
define void @hi1(i32* nocapture %x) #0 {
+; CHECK-LABEL: define void @hi1
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDVAR]] to i32
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[INDVAR]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP0]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -75,20 +93,6 @@ for.body: ; preds = %entry, %for.body
%cmp = icmp slt i32 %2, 1500
br i1 %cmp, label %for.body, label %for.end
-; CHECK-LABEL: @hi1
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %0 = trunc i64 %indvar to i32
-; CHECK: %call = tail call i32 @foo(i32 0) #1
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvar
-; CHECK: store i32 %call, i32* %arrayidx, align 4
-; CHECK: %indvar.next = add i64 %indvar, 1
-; CHECK: %exitcond = icmp eq i32 %0, 1499
-; CHECK: br i1 %exitcond, label %for.end, label %for.body
-
-; CHECK: ret
-
for.end: ; preds = %for.body
ret void
}
@@ -103,6 +107,21 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @hi2(i32* nocapture %x) #0 {
+; CHECK-LABEL: define void @hi2
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[INDVARS_IV]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -124,19 +143,6 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @hi2
-
-; CHECK: for.body:
-; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK: %call = tail call i32 @foo(i32 0) #1
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
-; CHECK: store i32 %call, i32* %arrayidx, align 4
-; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK: %exitcond1 = icmp eq i64 %indvars.iv, 1499
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
-
-; CHECK: ret
-
for.end: ; preds = %for.body
ret void
}
@@ -153,6 +159,26 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @goo(float %alpha, float* nocapture %a, float* nocapture readonly %b) #0 {
+; CHECK-LABEL: define void @goo
+; CHECK-SAME: (float [[ALPHA:%.*]], float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDVAR]] to i32
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP1]], [[ALPHA]]
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], [[MUL]]
+; CHECK-NEXT: store float [[ADD]], float* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP0]], 3199
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -202,24 +228,6 @@ for.body: ; preds = %entry, %for.body
%cmp = icmp slt i32 %14, 3200
br i1 %cmp, label %for.body, label %for.end
-; CHECK-LABEL: @goo
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %0 = trunc i64 %indvar to i32
-; CHECK: %arrayidx = getelementptr inbounds float, float* %b, i64 %indvar
-; CHECK: %1 = load float, float* %arrayidx, align 4
-; CHECK: %mul = fmul float %1, %alpha
-; CHECK: %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvar
-; CHECK: %2 = load float, float* %arrayidx2, align 4
-; CHECK: %add = fadd float %2, %mul
-; CHECK: store float %add, float* %arrayidx2, align 4
-; CHECK: %indvar.next = add i64 %indvar, 1
-; CHECK: %exitcond = icmp eq i32 %0, 3199
-; CHECK: br i1 %exitcond, label %for.end, label %for.body
-
-; CHECK: ret
-
for.end: ; preds = %for.body
ret void
}
@@ -236,6 +244,29 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @hoo(float %alpha, float* nocapture %a, float* nocapture readonly %b, i32* nocapture readonly %ip) #0 {
+; CHECK-LABEL: define void @hoo
+; CHECK-SAME: (float [[ALPHA:%.*]], float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], i32* nocapture readonly [[IP:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDVAR]] to i32
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[IP]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[IDXPROM1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP2]], [[ALPHA]]
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX4]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[MUL]]
+; CHECK-NEXT: store float [[ADD]], float* [[ARRAYIDX4]], align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP0]], 3199
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -300,26 +331,8 @@ for.body: ; preds = %entry, %for.body
%cmp = icmp slt i32 %19, 3200
br i1 %cmp, label %for.body, label %for.end
-; CHECK-LABEL: @hoo
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %0 = trunc i64 %indvar to i32
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %ip, i64 %indvar
-; CHECK: %1 = load i32, i32* %arrayidx, align 4
-; CHECK: %idxprom1 = sext i32 %1 to i64
-; CHECK: %arrayidx2 = getelementptr inbounds float, float* %b, i64 %idxprom1
-; CHECK: %2 = load float, float* %arrayidx2, align 4
-; CHECK: %mul = fmul float %2, %alpha
-; CHECK: %arrayidx4 = getelementptr inbounds float, float* %a, i64 %indvar
-; CHECK: %3 = load float, float* %arrayidx4, align 4
-; CHECK: %add = fadd float %3, %mul
-; CHECK: store float %add, float* %arrayidx4, align 4
-; CHECK: %indvar.next = add i64 %indvar, 1
-; CHECK: %exitcond = icmp eq i32 %0, 3199
-; CHECK: br i1 %exitcond, label %for.end, label %for.body
-
-; CHECK: ret
+
+
for.end: ; preds = %for.body
ret void
@@ -339,6 +352,24 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @multi1(i32* nocapture %x) #0 {
+; CHECK-LABEL: define void @multi1
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDVARS_IV]], 6
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[TMP0]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX6]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[INDVARS_IV]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%call = tail call i32 @foo(i32 0) #1
br label %for.body
@@ -367,18 +398,7 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @multi1
-; CHECK:for.body:
-; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK: %0 = add i64 %indvars.iv, 6
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
-; CHECK: store i32 %call, i32* %arrayidx, align 4
-; CHECK: %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %0
-; CHECK: store i32 %call, i32* %arrayidx6, align 4
-; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK: %exitcond1 = icmp eq i64 %indvars.iv, 1499
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
@@ -398,6 +418,24 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @multi2(i32* nocapture %x) #0 {
+; CHECK-LABEL: define void @multi2
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDVARS_IV]], 3
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[TMP0]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX6]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[INDVARS_IV]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%call = tail call i32 @foo(i32 0) #1
br label %for.body
@@ -427,18 +465,7 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @multi2
-; CHECK:for.body:
-; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK: %0 = add i64 %indvars.iv, 3
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
-; CHECK: store i32 %call, i32* %arrayidx, align 4
-; CHECK: %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %0
-; CHECK: store i32 %call, i32* %arrayidx6, align 4
-; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK: %exitcond1 = icmp eq i64 %indvars.iv, 1499
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
@@ -456,6 +483,22 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @multi3(i32* nocapture %x) #0 {
+; CHECK-LABEL: define void @multi3
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDVARS_IV]], 3
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 [[TMP0]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[INDVARS_IV]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%call = tail call i32 @foo(i32 0) #1
br label %for.body
@@ -477,15 +520,6 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @multi3
-; CHECK: for.body:
-; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK: %0 = add i64 %indvars.iv, 3
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %0
-; CHECK: store i32 %call, i32* %arrayidx, align 4
-; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK: %exitcond1 = icmp eq i64 %indvars.iv, 1499
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
@@ -502,6 +536,22 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @bar2(i32* nocapture readnone %x, i32 %y, i32 %z) #0 {
+; CHECK-LABEL: define void @bar2
+; CHECK-SAME: (i32* nocapture readnone [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDVAR]], [[Y]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[INDVAR]], [[Z]]
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 [[TMP3]]) #[[ATTR1]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i32 [[INDVAR]], 500
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -518,7 +568,7 @@ for.body: ; preds = %for.body, %entry
%tmp1a = add i32 %add, %y
%tmp3a = add i32 %tmp2a, %tmp1a
%calla = tail call i32 @foo(i32 %tmp3a) #1
-
+
%add2 = add nsw i32 %i.08, 2
%tmp2b = mul i32 %add2, %z
%tmp1b = add i32 %add2, %y
@@ -530,20 +580,6 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp sge i32 %add3, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @bar2
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %tmp1 = add i32 %indvar, %y
-; CHECK: %tmp2 = mul i32 %indvar, %z
-; CHECK: %tmp3 = add i32 %tmp2, %tmp1
-; CHECK: %call = tail call i32 @foo(i32 %tmp3) #1
-; CHECK: %indvar.next = add i32 %indvar, 1
-; CHECK: %exitcond1 = icmp eq i32 %indvar, 500
-; CHECK: br i1 %exitcond1, label %for.end, label %for.body
-
-; CHECK: ret
-
for.end: ; preds = %for.body
ret void
}
@@ -552,6 +588,28 @@ for.end: ; preds = %for.body
; Function Attrs: nounwind uwtable
define void @gep1(%struct.s* nocapture %x) #0 {
+; CHECK-LABEL: define void @gep1
+; CHECK-SAME: (%struct.s* nocapture [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = mul nsw i64 [[INDVARS_IV]], 3
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.s* [[X]], i64 [[TMP0]], i32 0
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[TMP0]], 1
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[X]], i64 [[TMP1]], i32 0
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX4]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = add nsw i64 [[TMP0]], 2
+; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[X]], i64 [[TMP2]], i32 0
+; CHECK-NEXT: store i32 [[CALL]], i32* [[ARRAYIDX9]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 500
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%call = tail call i32 @foo(i32 0) #1
br label %for.body
@@ -571,14 +629,27 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @gep1
; This test is a crash test only.
-; CHECK: ret
for.end: ; preds = %for.body
ret void
}
define void @gep-indexing(i32* nocapture %x) {
+; CHECK-LABEL: define void @gep-indexing
+; CHECK-SAME: (i32* nocapture [[X:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 0) #[[ATTR1]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[X]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i32 [[CALL]], i32* [[SCEVGEP]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp eq i64 [[INDVARS_IV]], 1499
+; CHECK-NEXT: br i1 [[EXITCOND1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%call = tail call i32 @foo(i32 0) #1
br label %for.body
@@ -596,33 +667,28 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @gep-indexing
-; CHECK: for.body:
-; CHECK-NEXT: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK-NEXT: %scevgep = getelementptr i32, i32* %x, i64 %indvars.iv
-; CHECK-NEXT: store i32 %call, i32* %scevgep, align 4
-; CHECK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK-NEXT: %exitcond1 = icmp eq i64 %indvars.iv, 1499
-; CHECK-NEXT: br i1 %exitcond1, label %for.end, label %for.body
-
for.end: ; preds = %for.body
ret void
}
define void @unordered_atomic_ops(i32* noalias %buf_0, i32* noalias %buf_1) {
-; CHECK-LABEL: @unordered_atomic_ops(
-
-; CHECK: for.body:
-; CHECK-NEXT: %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK-NEXT: %buf0_a = getelementptr i32, i32* %buf_0, i32 %indvar
-; CHECK-NEXT: %buf1_a = getelementptr i32, i32* %buf_1, i32 %indvar
-; CHECK-NEXT: %va = load atomic i32, i32* %buf0_a unordered, align 4
-; CHECK-NEXT: store atomic i32 %va, i32* %buf1_a unordered, align 4
-; CHECK-NEXT: %indvar.next = add i32 %indvar, 1
-; CHECK-NEXT: %exitcond = icmp eq i32 %indvar, 3199
-; CHECK-NEXT: br i1 %exitcond, label %for.end, label %for.body
-
+; CHECK-LABEL: define void @unordered_atomic_ops
+; CHECK-SAME: (i32* noalias [[BUF_0:%.*]], i32* noalias [[BUF_1:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BUF0_A:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVAR]]
+; CHECK-NEXT: [[BUF1_A:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVAR]]
+; CHECK-NEXT: [[VA:%.*]] = load atomic i32, i32* [[BUF0_A]] unordered, align 4
+; CHECK-NEXT: store atomic i32 [[VA]], i32* [[BUF1_A]] unordered, align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVAR]], 3199
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -647,17 +713,31 @@ for.end:
define void @unordered_atomic_ops_nomatch(i32* noalias %buf_0, i32* noalias %buf_1) {
; Negative test
-
-; CHECK-LABEL: @unordered_atomic_ops_nomatch(
+; CHECK-LABEL: define void @unordered_atomic_ops_nomatch
+; CHECK-SAME: (i32* noalias [[BUF_0:%.*]], i32* noalias [[BUF_1:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 2
+; CHECK-NEXT: [[INDVARS_MID:%.*]] = add i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[BUF0_A:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF0_B:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[BUF1_A:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF1_B:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[VA:%.*]] = load atomic i32, i32* [[BUF0_A]] unordered, align 4
+; CHECK-NEXT: [[VB:%.*]] = load atomic i32, i32* [[BUF0_B]] unordered, align 4
+; CHECK-NEXT: store i32 [[VA]], i32* [[BUF1_A]], align 4
+; CHECK-NEXT: store atomic i32 [[VB]], i32* [[BUF1_B]] unordered, align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INDVARS_IV_NEXT]], 3200
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
for.body:
-; CHECK: for.body:
-; CHECK: %indvars.iv.next = add i32 %indvars.iv, 2
-; CHECK: %indvars.mid = add i32 %indvars.iv, 1
-; CHECK: %cmp = icmp slt i32 %indvars.iv.next, 3200
-; CHECK: br i1 %cmp, label %for.body, label %for.end
%indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%indvars.iv.next = add i32 %indvars.iv, 2
@@ -679,17 +759,31 @@ for.end:
define void @ordered_atomic_ops(i32* noalias %buf_0, i32* noalias %buf_1) {
; Negative test
-
-; CHECK-LABEL: @ordered_atomic_ops(
+; CHECK-LABEL: define void @ordered_atomic_ops
+; CHECK-SAME: (i32* noalias [[BUF_0:%.*]], i32* noalias [[BUF_1:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 2
+; CHECK-NEXT: [[INDVARS_MID:%.*]] = add i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[BUF0_A:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF0_B:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[BUF1_A:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF1_B:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[VA:%.*]] = load atomic i32, i32* [[BUF0_A]] acquire, align 4
+; CHECK-NEXT: [[VB:%.*]] = load atomic i32, i32* [[BUF0_B]] acquire, align 4
+; CHECK-NEXT: store atomic i32 [[VA]], i32* [[BUF1_A]] release, align 4
+; CHECK-NEXT: store atomic i32 [[VB]], i32* [[BUF1_B]] release, align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INDVARS_IV_NEXT]], 3200
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
for.body:
-; CHECK: for.body:
-; CHECK: %indvars.iv.next = add i32 %indvars.iv, 2
-; CHECK: %indvars.mid = add i32 %indvars.iv, 1
-; CHECK: %cmp = icmp slt i32 %indvars.iv.next, 3200
-; CHECK: br i1 %cmp, label %for.body, label %for.end
%indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%indvars.iv.next = add i32 %indvars.iv, 2
@@ -710,17 +804,32 @@ for.end:
}
define void @unordered_atomic_ops_with_fence(i32* noalias %buf_0, i32* noalias %buf_1) {
-; CHECK-LABEL: @unordered_atomic_ops_with_fence(
+; CHECK-LABEL: define void @unordered_atomic_ops_with_fence
+; CHECK-SAME: (i32* noalias [[BUF_0:%.*]], i32* noalias [[BUF_1:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 2
+; CHECK-NEXT: [[INDVARS_MID:%.*]] = add i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[BUF0_A:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF0_B:%.*]] = getelementptr i32, i32* [[BUF_0]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[BUF1_A:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_IV]]
+; CHECK-NEXT: [[BUF1_B:%.*]] = getelementptr i32, i32* [[BUF_1]], i32 [[INDVARS_MID]]
+; CHECK-NEXT: [[VA:%.*]] = load atomic i32, i32* [[BUF0_A]] unordered, align 4
+; CHECK-NEXT: [[VB:%.*]] = load atomic i32, i32* [[BUF0_B]] unordered, align 4
+; CHECK-NEXT: fence seq_cst
+; CHECK-NEXT: store atomic i32 [[VA]], i32* [[BUF1_A]] unordered, align 4
+; CHECK-NEXT: store atomic i32 [[VB]], i32* [[BUF1_B]] unordered, align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INDVARS_IV_NEXT]], 3200
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
for.body:
-; CHECK: for.body:
-; CHECK: %va = load atomic i32, i32* %buf0_a unordered, align 4
-; CHECK-NEXT: %vb = load atomic i32, i32* %buf0_b unordered, align 4
-; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: store atomic i32 %va, i32* %buf1_a unordered, align 4
-; CHECK-NEXT: store atomic i32 %vb, i32* %buf1_b unordered, align 4
%indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%indvars.iv.next = add i32 %indvars.iv, 2
@@ -742,50 +851,77 @@ for.end:
}
define void @pointer_bitcast_baseinst(i16* %arg, i8* %arg1, i64 %arg2) {
-; CHECK-LABEL: @pointer_bitcast_baseinst(
+; CHECK-LABEL: define void @pointer_bitcast_baseinst
+; CHECK-SAME: (i16* [[ARG:%.*]], i8* [[ARG1:%.*]], i64 [[ARG2:%.*]]) {
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[ARG2]], -17
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 4
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb3:
-; CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %bb3 ], [ 0, %bb ]
-; CHECK-NEXT: %4 = shl nuw i64 %indvar, 3
-; CHECK-NEXT: %5 = add i64 %4, 1
-; CHECK-NEXT: %tmp5 = shl nuw i64 %5, 1
-; CHECK-NEXT: %tmp6 = getelementptr i8, i8* %arg1, i64 %tmp5
-; CHECK-NEXT: %tmp7 = bitcast i8* %tmp6 to <8 x i16>*
-; CHECK-NEXT: %tmp8 = load <8 x i16>, <8 x i16>* %tmp7, align 2
-; CHECK-NEXT: %tmp13 = getelementptr i16, i16* %arg, i64 %5
-; CHECK-NEXT: %tmp14 = bitcast i16* %tmp13 to <8 x i16>*
-; CHECK-NEXT: store <8 x i16> %tmp8, <8 x i16>* %tmp14, align 2
-; CHECK-NEXT: %indvar.next = add i64 %indvar, 1
-; CHECK-NEXT: %exitcond = icmp eq i64 %indvar, %3
-; CHECK-NEXT: br i1 %exitcond, label %bb19, label %bb3
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[BB3]] ], [ 0, [[BB:%.*]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[INDVAR]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[INST5:%.*]] = shl nuw i64 [[TMP5]], 1
+; CHECK-NEXT: [[INST6:%.*]] = getelementptr i8, i8* [[ARG1]], i64 [[INST5]]
+; CHECK-NEXT: [[INST7:%.*]] = bitcast i8* [[INST6]] to <8 x i16>*
+; CHECK-NEXT: [[INST8:%.*]] = load <8 x i16>, <8 x i16>* [[INST7]], align 2
+; CHECK-NEXT: [[INST13:%.*]] = getelementptr i16, i16* [[ARG]], i64 [[TMP5]]
+; CHECK-NEXT: [[INST14:%.*]] = bitcast i16* [[INST13]] to <8 x i16>*
+; CHECK-NEXT: store <8 x i16> [[INST8]], <8 x i16>* [[INST14]], align 2
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR]], [[TMP3]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB19:%.*]], label [[BB3]]
+; CHECK: bb19:
+; CHECK-NEXT: ret void
+;
bb:
br label %bb3
bb3: ; preds = %bb3, %bb
- %tmp = phi i64 [ 1, %bb ], [ %tmp17, %bb3 ]
- %tmp4 = add nuw i64 %tmp, 8
- %tmp5 = shl nuw i64 %tmp, 1
- %tmp6 = getelementptr i8, i8* %arg1, i64 %tmp5
- %tmp7 = bitcast i8* %tmp6 to <8 x i16>*
- %tmp8 = load <8 x i16>, <8 x i16>* %tmp7, align 2
- %tmp9 = shl i64 %tmp4, 1
- %tmp10 = getelementptr i8, i8* %arg1, i64 %tmp9
- %tmp11 = bitcast i8* %tmp10 to <8 x i16>*
- %tmp12 = load <8 x i16>, <8 x i16>* %tmp11, align 2
- %tmp13 = getelementptr i16, i16* %arg, i64 %tmp
- %tmp14 = bitcast i16* %tmp13 to <8 x i16>*
- store <8 x i16> %tmp8, <8 x i16>* %tmp14, align 2
- %tmp15 = getelementptr i16, i16* %arg, i64 %tmp4
- %tmp16 = bitcast i16* %tmp15 to <8 x i16>*
- store <8 x i16> %tmp12, <8 x i16>* %tmp16, align 2
- %tmp17 = add nuw nsw i64 %tmp, 16
- %tmp18 = icmp eq i64 %tmp17, %arg2
- br i1 %tmp18, label %bb19, label %bb3
+ %inst = phi i64 [ 1, %bb ], [ %inst17, %bb3 ]
+ %inst4 = add nuw i64 %inst, 8
+ %inst5 = shl nuw i64 %inst, 1
+ %inst6 = getelementptr i8, i8* %arg1, i64 %inst5
+ %inst7 = bitcast i8* %inst6 to <8 x i16>*
+ %inst8 = load <8 x i16>, <8 x i16>* %inst7, align 2
+ %inst9 = shl i64 %inst4, 1
+ %inst10 = getelementptr i8, i8* %arg1, i64 %inst9
+ %inst11 = bitcast i8* %inst10 to <8 x i16>*
+ %inst12 = load <8 x i16>, <8 x i16>* %inst11, align 2
+ %inst13 = getelementptr i16, i16* %arg, i64 %inst
+ %inst14 = bitcast i16* %inst13 to <8 x i16>*
+ store <8 x i16> %inst8, <8 x i16>* %inst14, align 2
+ %inst15 = getelementptr i16, i16* %arg, i64 %inst4
+ %inst16 = bitcast i16* %inst15 to <8 x i16>*
+ store <8 x i16> %inst12, <8 x i16>* %inst16, align 2
+ %inst17 = add nuw nsw i64 %inst, 16
+ %inst18 = icmp eq i64 %inst17, %arg2
+ br i1 %inst18, label %bb19, label %bb3
bb19: ; preds = %bb3
ret void
}
define void @bad_step(i32* nocapture readnone %x) #0 {
+; CHECK-LABEL: define void @bad_step
+; CHECK-SAME: (i32* nocapture readnone [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD3:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @foo(i32 [[I_08]]) #[[ATTR1]]
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I_08]], 2
+; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @foo(i32 [[ADD]]) #[[ATTR1]]
+; CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[I_08]], 3
+; CHECK-NEXT: [[CALL3:%.*]] = tail call i32 @foo(i32 [[ADD2]]) #[[ATTR1]]
+; CHECK-NEXT: [[ADD3]] = add nsw i32 [[I_08]], 6
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp sge i32 [[ADD3]], 500
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -800,10 +936,6 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp sge i32 %add3, 500
br i1 %exitcond, label %for.end, label %for.body
-; CHECK-LABEL: @bad_step
-; CHECK: %add = add nsw i32 %i.08, 2
-; CHECK: %add2 = add nsw i32 %i.08, 3
-; CHECK: %add3 = add nsw i32 %i.08, 6
for.end: ; preds = %for.body
ret void
@@ -813,7 +945,21 @@ for.end: ; preds = %for.body
@b = external global [512 x [4 x i64]], align 16
define void @ptr_step_crash() {
-; CHECK-LABEL: @ptr_step_crash(
+; CHECK-LABEL: define void @ptr_step_crash() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY42_3:%.*]]
+; CHECK: for.body42.3:
+; CHECK-NEXT: [[K_2207_3:%.*]] = phi i32 [ -512, [[ENTRY:%.*]] ], [ [[INC63_3:%.*]], [[FOR_BODY42_3]] ]
+; CHECK-NEXT: [[SUB46_3:%.*]] = add nsw i32 [[K_2207_3]], 512
+; CHECK-NEXT: [[IDXPROM47_3:%.*]] = zext i32 [[SUB46_3]] to i64
+; CHECK-NEXT: [[ARRAYIDX48_3:%.*]] = getelementptr inbounds [2 x [512 x i64]], [2 x [512 x i64]]* @a, i64 0, i64 0, i64 [[IDXPROM47_3]]
+; CHECK-NEXT: [[ARRAYIDX55_3:%.*]] = getelementptr inbounds [512 x [4 x i64]], [512 x [4 x i64]]* @b, i64 0, i64 [[IDXPROM47_3]], i64 3
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[ARRAYIDX55_3]], align 8
+; CHECK-NEXT: [[INC63_3]] = add nsw i32 [[K_2207_3]], 1
+; CHECK-NEXT: br i1 true, label [[FOR_INC65_3:%.*]], label [[FOR_BODY42_3]]
+; CHECK: for.inc65.3:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body42.3
diff --git a/llvm/test/Transforms/LoopReroll/extra_instr.ll b/llvm/test/Transforms/LoopReroll/extra_instr.ll
index 84ebec10048aa..dfb87f7f01c6c 100644
--- a/llvm/test/Transforms/LoopReroll/extra_instr.ll
+++ b/llvm/test/Transforms/LoopReroll/extra_instr.ll
@@ -1,18 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -opaque-pointers=0 -S -passes=loop-reroll %s | FileCheck %s
target triple = "aarch64--linux-gnu"
define void @rerollable1([2 x i32]* nocapture %a) {
+; CHECK-LABEL: define void @rerollable1
+; CHECK-SAME: ([2 x i32]* nocapture [[A:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr [2 x i32], [2 x i32]* [[A]], i64 20, i64 [[IV]]
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr [2 x i32], [2 x i32]* [[A]], i64 10, i64 [[IV]]
+; CHECK-NEXT: [[VALUE0:%.*]] = load i32, i32* [[SCEVGEP1]], align 4
+; CHECK-NEXT: store i32 [[VALUE0]], i32* [[SCEVGEP]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[IV]], 9
+; CHECK-NEXT: br i1 [[EXITCOND2]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
loop:
-; CHECK-LABEL: loop:
-; CHECK-NEXT: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
-; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr [2 x i32], [2 x i32]* %a, i64 20, i64 %iv
-; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr [2 x i32], [2 x i32]* %a, i64 10, i64 %iv
-; CHECK-NEXT: [[VALUE:%.*]] = load i32, i32* [[SCEVGEP1]], align 4
-; CHECK-NEXT: store i32 [[VALUE]], i32* [[SCEVGEP2]], align 4
; base instruction
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
@@ -47,15 +58,35 @@ exit:
}
define void @unrerollable1([2 x i32]* nocapture %a) {
+; CHECK-LABEL: define void @unrerollable1
+; CHECK-SAME: ([2 x i32]* nocapture [[A:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[STPTRX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[IV]], i64 0
+; CHECK-NEXT: store i32 999, i32* [[STPTRX]], align 4
+; CHECK-NEXT: [[PLUS20:%.*]] = add nuw nsw i64 [[IV]], 20
+; CHECK-NEXT: [[PLUS10:%.*]] = add nuw nsw i64 [[IV]], 10
+; CHECK-NEXT: [[LDPTR0:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS20]], i64 0
+; CHECK-NEXT: [[VALUE0:%.*]] = load i32, i32* [[LDPTR0]], align 4
+; CHECK-NEXT: [[STPTR0:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS10]], i64 0
+; CHECK-NEXT: store i32 [[VALUE0]], i32* [[STPTR0]], align 4
+; CHECK-NEXT: [[LDPTR1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS20]], i64 1
+; CHECK-NEXT: [[VALUE1:%.*]] = load i32, i32* [[LDPTR1]], align 4
+; CHECK-NEXT: [[STPTR1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS10]], i64 1
+; CHECK-NEXT: store i32 [[VALUE1]], i32* [[STPTR1]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 5
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
loop:
-; CHECK-LABEL: loop:
-; CHECK-NEXT: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
-; CHECK-NEXT: %stptrx = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %iv, i64 0
-; CHECK-NEXT: store i32 999, i32* %stptrx, align 4
; base instruction
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
@@ -92,16 +123,35 @@ exit:
}
define void @unrerollable2([2 x i32]* nocapture %a) {
+; CHECK-LABEL: define void @unrerollable2
+; CHECK-SAME: ([2 x i32]* nocapture [[A:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[STPTRX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[IV_NEXT]], i64 0
+; CHECK-NEXT: store i32 999, i32* [[STPTRX]], align 4
+; CHECK-NEXT: [[PLUS20:%.*]] = add nuw nsw i64 [[IV]], 20
+; CHECK-NEXT: [[PLUS10:%.*]] = add nuw nsw i64 [[IV]], 10
+; CHECK-NEXT: [[LDPTR0:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS20]], i64 0
+; CHECK-NEXT: [[VALUE0:%.*]] = load i32, i32* [[LDPTR0]], align 4
+; CHECK-NEXT: [[STPTR0:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS10]], i64 0
+; CHECK-NEXT: store i32 [[VALUE0]], i32* [[STPTR0]], align 4
+; CHECK-NEXT: [[LDPTR1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS20]], i64 1
+; CHECK-NEXT: [[VALUE1:%.*]] = load i32, i32* [[LDPTR1]], align 4
+; CHECK-NEXT: [[STPTR1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 [[PLUS10]], i64 1
+; CHECK-NEXT: store i32 [[VALUE1]], i32* [[STPTR1]], align 4
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 5
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
loop:
-; CHECK-LABEL: loop:
-; CHECK-NEXT: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
-; CHECK-NEXT: %iv.next = add nuw nsw i64 %iv, 1
-; CHECK-NEXT: %stptrx = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %iv.next, i64 0
-; CHECK-NEXT: store i32 999, i32* %stptrx, align 4
; base instruction
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
@@ -138,15 +188,28 @@ exit:
}
define dso_local void @rerollable2() {
+; CHECK-LABEL: define dso_local void @rerollable2() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[IV]], 24
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[IV]], 20
+; CHECK-NEXT: [[IV_SCALED_DIV5:%.*]] = udiv i32 [[TMP1]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD4_DIV5:%.*]] = udiv i32 [[TMP0]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD4_DIV5]])
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[IV]], 8
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
loop:
-; CHECK-LABEL: loop:
-; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
-; CHECK-NEXT: {{%.*}} = add i32 %iv, {{20|24}}
-; CHECK-NEXT: {{%.*}} = add i32 %iv, {{20|24}}
; induction variable
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
@@ -200,17 +263,43 @@ exit:
}
define dso_local void @unrerollable3() {
+; CHECK-LABEL: define dso_local void @unrerollable3() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[IV_MUL3:%.*]] = mul nuw nsw i32 [[IV]], 3
+; CHECK-NEXT: [[IV_SCALED:%.*]] = add nuw nsw i32 [[IV_MUL3]], 20
+; CHECK-NEXT: [[IV_MUL7:%.*]] = mul nuw nsw i32 [[IV]], 7
+; CHECK-NEXT: tail call void @bar(i32 [[IV_MUL7]])
+; CHECK-NEXT: [[IV_SCALED_DIV5:%.*]] = udiv i32 [[IV_SCALED]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD1:%.*]] = add nuw nsw i32 [[IV_SCALED]], 1
+; CHECK-NEXT: [[IV_SCALED_ADD1_DIV5:%.*]] = udiv i32 [[IV_SCALED_ADD1]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD1_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD2:%.*]] = add nuw nsw i32 [[IV_SCALED]], 2
+; CHECK-NEXT: [[IV_SCALED_ADD2_DIV5:%.*]] = udiv i32 [[IV_SCALED_ADD2]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD2_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD4:%.*]] = add nuw nsw i32 [[IV_SCALED]], 4
+; CHECK-NEXT: [[IV_SCALED_ADD4_DIV5:%.*]] = udiv i32 [[IV_SCALED_ADD4]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD4_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD5:%.*]] = add nuw nsw i32 [[IV_SCALED]], 5
+; CHECK-NEXT: [[IV_SCALED_ADD5_DIV5:%.*]] = udiv i32 [[IV_SCALED_ADD5]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD5_DIV5]])
+; CHECK-NEXT: [[IV_SCALED_ADD6:%.*]] = add nuw nsw i32 [[IV_SCALED]], 6
+; CHECK-NEXT: [[IV_SCALED_ADD6_DIV5:%.*]] = udiv i32 [[IV_SCALED_ADD6]], 5
+; CHECK-NEXT: tail call void @bar(i32 [[IV_SCALED_ADD6_DIV5]])
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IV_NEXT]], 3
+; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
loop:
-; CHECK-LABEL: loop:
-; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
-; CHECK-NEXT: %iv.mul3 = mul nuw nsw i32 %iv, 3
-; CHECK-NEXT: %iv.scaled = add nuw nsw i32 %iv.mul3, 20
-; CHECK-NEXT: %iv.mul7 = mul nuw nsw i32 %iv, 7
-; CHECK-NEXT: tail call void @bar(i32 %iv.mul7)
; induction variable
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
diff --git a/llvm/test/Transforms/LoopReroll/ptrindvar.ll b/llvm/test/Transforms/LoopReroll/ptrindvar.ll
index a61724a07c617..020eb91654c3a 100644
--- a/llvm/test/Transforms/LoopReroll/ptrindvar.ll
+++ b/llvm/test/Transforms/LoopReroll/ptrindvar.ll
@@ -1,7 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -opaque-pointers=0 -S -passes=loop-reroll %s | FileCheck %s
target triple = "aarch64--linux-gnu"
define i32 @test(i32* readonly %buf, i32* readnone %end) #0 {
+; CHECK-LABEL: define i32 @test
+; CHECK-SAME: (i32* readonly [[BUF:%.*]], i32* readnone [[END:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[BUF2:%.*]] = ptrtoint i32* [[BUF]] to i64
+; CHECK-NEXT: [[END1:%.*]] = ptrtoint i32* [[END]] to i64
+; CHECK-NEXT: [[CMP_9:%.*]] = icmp eq i32* [[BUF]], [[END]]
+; CHECK-NEXT: br i1 [[CMP_9]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
+; CHECK: while.body.preheader:
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BUF2]]
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
+; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
+; CHECK: while.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[S_011:%.*]] = phi i32 [ [[ADD:%.*]], [[WHILE_BODY]] ], [ undef, [[WHILE_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[BUF]], i64 [[INDVAR]]
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[SCEVGEP]], align 4
+; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP5]], [[S_011]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR]], [[TMP4]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[WHILE_END_LOOPEXIT:%.*]], label [[WHILE_BODY]]
+; CHECK: while.end.loopexit:
+; CHECK-NEXT: [[ADD2_LCSSA:%.*]] = phi i32 [ [[ADD]], [[WHILE_BODY]] ]
+; CHECK-NEXT: br label [[WHILE_END]]
+; CHECK: while.end:
+; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[ADD2_LCSSA]], [[WHILE_END_LOOPEXIT]] ]
+; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
+;
entry:
%cmp.9 = icmp eq i32* %buf, %end
br i1 %cmp.9, label %while.end, label %while.body.preheader
@@ -10,15 +41,6 @@ while.body.preheader:
br label %while.body
while.body:
-;CHECK-LABEL: while.body:
-;CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %while.body ], [ 0, %while.body.preheader ]
-;CHECK-NEXT: %S.011 = phi i32 [ %add, %while.body ], [ undef, %while.body.preheader ]
-;CHECK-NEXT: %scevgep = getelementptr i32, i32* %buf, i64 %indvar
-;CHECK-NEXT: %5 = load i32, i32* %scevgep, align 4
-;CHECK-NEXT: %add = add nsw i32 %5, %S.011
-;CHECK-NEXT: %indvar.next = add i64 %indvar, 1
-;CHECK-NEXT: %exitcond = icmp eq i64 %indvar, %4
-;CHECK-NEXT: br i1 %exitcond, label %while.end.loopexit, label %while.body
%S.011 = phi i32 [ %add2, %while.body ], [ undef, %while.body.preheader ]
%buf.addr.010 = phi i32* [ %add.ptr, %while.body ], [ %buf, %while.body.preheader ]
@@ -41,6 +63,37 @@ while.end:
}
define i32 @test2(i32* readonly %buf, i32* readnone %end) #0 {
+; CHECK-LABEL: define i32 @test2
+; CHECK-SAME: (i32* readonly [[BUF:%.*]], i32* readnone [[END:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[END2:%.*]] = ptrtoint i32* [[END]] to i64
+; CHECK-NEXT: [[BUF1:%.*]] = ptrtoint i32* [[BUF]] to i64
+; CHECK-NEXT: [[CMP_9:%.*]] = icmp eq i32* [[BUF]], [[END]]
+; CHECK-NEXT: br i1 [[CMP_9]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
+; CHECK: while.body.preheader:
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[BUF1]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[END2]]
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
+; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
+; CHECK: while.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[S_011:%.*]] = phi i32 [ [[ADD:%.*]], [[WHILE_BODY]] ], [ undef, [[WHILE_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = mul nsw i64 [[INDVAR]], -1
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[BUF]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[SCEVGEP]], align 4
+; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP6]], [[S_011]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR]], [[TMP4]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[WHILE_END_LOOPEXIT:%.*]], label [[WHILE_BODY]]
+; CHECK: while.end.loopexit:
+; CHECK-NEXT: [[ADD2_LCSSA:%.*]] = phi i32 [ [[ADD]], [[WHILE_BODY]] ]
+; CHECK-NEXT: br label [[WHILE_END]]
+; CHECK: while.end:
+; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[ADD2_LCSSA]], [[WHILE_END_LOOPEXIT]] ]
+; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
+;
entry:
%cmp.9 = icmp eq i32* %buf, %end
br i1 %cmp.9, label %while.end, label %while.body.preheader
@@ -49,16 +102,6 @@ while.body.preheader:
br label %while.body
while.body:
-;CHECK-LABEL: while.body:
-;CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %while.body ], [ 0, %while.body.preheader ]
-;CHECK-NEXT: %S.011 = phi i32 [ %add, %while.body ], [ undef, %while.body.preheader ]
-;CHECK-NEXT: %5 = mul nsw i64 %indvar, -1
-;CHECK-NEXT: %scevgep = getelementptr i32, i32* %buf, i64 %5
-;CHECK-NEXT: %6 = load i32, i32* %scevgep, align 4
-;CHECK-NEXT: %add = add nsw i32 %6, %S.011
-;CHECK-NEXT: %indvar.next = add i64 %indvar, 1
-;CHECK-NEXT: %exitcond = icmp eq i64 %indvar, %4
-;CHECK-NEXT: br i1 %exitcond, label %while.end.loopexit, label %while.body
%S.011 = phi i32 [ %add2, %while.body ], [ undef, %while.body.preheader ]
%buf.addr.010 = phi i32* [ %add.ptr, %while.body ], [ %buf, %while.body.preheader ]
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