[PATCH] D149127: [RISCV] Add missing constraints for vwsll

[Brandon Wu via Phabricator via llvm-commits]

4vtomat updated this revision to Diff 516694.
4vtomat added a comment.

Resolved Craig's comment:

- Added invalid instruction test case for vwsll


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149127/new/

https://reviews.llvm.org/D149127

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/MC/RISCV/rvv/zvbb-invalid.s


Index: llvm/test/MC/RISCV/rvv/zvbb-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvbb-invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvbb %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vwsll.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vv v2, v2, v4
+
+vwsll.vx v2, v2, x10
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vx v2, v2, x10
+
+vwsll.vi v2, v2, 1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vi v2, v2, 1
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -138,6 +138,7 @@
   def  VREV8_V  : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
   defm VROL_V   : VALU_IV_V_X<"vrol", 0b010101>;
   defm VROR_V   : VROR_IV_V_X_I<"vror", 0b010100>;
+  let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
   defm VWSLL_V  : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>;
 } // Predicates = [HasStdExtZvbb]
 


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