[llvm] 075202d - [X86 isel] Fix permute mask calculation in lowerShuffleAsUNPCKAndPermute
Han Zhu via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 24 13:56:05 PDT 2023
Author: Han Zhu
Date: 2023-04-24T13:54:37-07:00
New Revision: 075202d126dfba6fd1503926808a2fcafab1714a
URL: https://github.com/llvm/llvm-project/commit/075202d126dfba6fd1503926808a2fcafab1714a
DIFF: https://github.com/llvm/llvm-project/commit/075202d126dfba6fd1503926808a2fcafab1714a.diff
LOG: [X86 isel] Fix permute mask calculation in lowerShuffleAsUNPCKAndPermute
This fixes [issue 62242](https://github.com/llvm/llvm-project/issues/62242)
This code block can potentially swap the order of V1 and V2 in Ops and therefore
also in the unpck instruction generated.
```
SDValue &Op = Ops[Elt & 1];
if (M < NumElts && (Op.isUndef() || Op == V1))
Op = V1;
else if (NumElts <= M && (Op.isUndef() || Op == V2)) {
Op = V2;
NormM -= NumElts;
} else
return SDValue();
```
But the permute mask is calculated assuming the first operand being V1 and
second V2, therefore causing a mis-compile.
First check if the input operands are swapped, and then calculate the permute
mask based on that.
Differential Revision: https://reviews.llvm.org/D148843
Added:
llvm/test/CodeGen/X86/pr62242.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7ec6175712a4..d5fdd233d82b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13332,12 +13332,20 @@ static SDValue lowerShuffleAsUNPCKAndPermute(const SDLoc &DL, MVT VT,
SmallVector<int, 32> PermuteMask(NumElts, -1);
for (int Elt = 0; Elt != NumElts; ++Elt) {
int M = Mask[Elt];
+ if (M < 0)
+ continue;
+ int NormM = M;
if (NumElts <= M)
- PermuteMask[Elt] = NumLaneElts * ((M - NumElts) / NumLaneElts) +
- (2 * (M % NumHalfLaneElts)) + 1;
- else if (0 <= M)
- PermuteMask[Elt] =
- NumLaneElts * (M / NumLaneElts) + (2 * (M % NumHalfLaneElts));
+ NormM -= NumElts;
+ bool IsFirstOp = M < NumElts;
+ int BaseMaskElt =
+ NumLaneElts * (NormM / NumLaneElts) + (2 * (NormM % NumHalfLaneElts));
+ if ((IsFirstOp && V1 == Ops[0]) || (!IsFirstOp && V2 == Ops[0]))
+ PermuteMask[Elt] = BaseMaskElt;
+ else if ((IsFirstOp && V1 == Ops[1]) || (!IsFirstOp && V2 == Ops[1]))
+ PermuteMask[Elt] = BaseMaskElt + 1;
+ assert(PermuteMask[Elt] != -1 &&
+ "Input mask element is defined but failed to assign permute mask");
}
unsigned UnpckOp = MatchLo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
diff --git a/llvm/test/CodeGen/X86/pr62242.ll b/llvm/test/CodeGen/X86/pr62242.ll
new file mode 100644
index 000000000000..2753a18bfc12
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr62242.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
+
+define <4 x i32> @unpck_permute_canonicalized_mask(<4 x i32> %a, <4 x i32> %b) {
+; AVX2-LABEL: unpck_permute_canonicalized_mask:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3,2,1]
+; AVX2-NEXT: retq
+ ; This mask will get canonicalized to vector_shuffle<6, 3, -1, 2> %b, %a.
+ ; Make sure the generated permute masks are still correct.
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 undef, i32 6>
+ ret <4 x i32> %shuffle
+}
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
index be54bf12a43a..0a28126d1b3a 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
@@ -165,7 +165,7 @@ define void @store_i32_stride5_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX1-ONLY-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm5
; AVX1-ONLY-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm6
; AVX1-ONLY-NEXT: vunpcklps {{.*#+}} ymm5 = ymm5[0],ymm6[0],ymm5[1],ymm6[1],ymm5[4],ymm6[4],ymm5[5],ymm6[5]
-; AVX1-ONLY-NEXT: vpermilps {{.*#+}} ymm5 = ymm5[u,u,1,0,u,u,u,6]
+; AVX1-ONLY-NEXT: vshufpd {{.*#+}} ymm5 = ymm5[0,0,2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
; AVX1-ONLY-NEXT: vunpcklps {{.*#+}} ymm7 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[4],ymm1[4],ymm4[5],ymm1[5]
; AVX1-ONLY-NEXT: vshufpd {{.*#+}} ymm7 = ymm7[0,0,3,3]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
index 6f0919967a5d..04bc4e5da890 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
@@ -205,12 +205,12 @@ define void @store_i8_stride5_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
define void @store_i8_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecptr2, ptr %in.vecptr3, ptr %in.vecptr4, ptr %out.vec) nounwind {
; SSE-LABEL: store_i8_stride5_vf8:
; SSE: # %bb.0:
-; SSE-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
+; SSE-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
; SSE-NEXT: movq {{.*#+}} xmm4 = mem[0],zero
; SSE-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,1,1]
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,1,1]
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [65535,65535,0,65535,0,65535,65535,0]
; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm3[2,1,2,3]
@@ -225,8 +225,8 @@ define void @store_i8_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: movdqa {{.*#+}} xmm6 = [255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255]
; SSE-NEXT: movdqa %xmm6, %xmm10
; SSE-NEXT: pandn %xmm5, %xmm10
-; SSE-NEXT: movdqa %xmm1, %xmm7
-; SSE-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm1[0],xmm7[1],xmm1[1],xmm7[2],xmm1[2],xmm7[3],xmm1[3],xmm7[4],xmm1[4],xmm7[5],xmm1[5],xmm7[6],xmm1[6],xmm7[7],xmm1[7]
+; SSE-NEXT: movdqa %xmm2, %xmm7
+; SSE-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm2[0],xmm7[1],xmm2[1],xmm7[2],xmm2[2],xmm7[3],xmm2[3],xmm7[4],xmm2[4],xmm7[5],xmm2[5],xmm7[6],xmm2[6],xmm7[7],xmm2[7]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[3,1,0,3,4,5,6,7]
; SSE-NEXT: pshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,6,6]
@@ -249,7 +249,7 @@ define void @store_i8_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: pandn %xmm10, %xmm8
; SSE-NEXT: por %xmm9, %xmm8
; SSE-NEXT: movdqa {{.*#+}} xmm9 = [255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255]
-; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm2[0,0,0,0]
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm1[0,0,0,0]
; SSE-NEXT: pand %xmm6, %xmm10
; SSE-NEXT: pshuflw {{.*#+}} xmm7 = xmm7[0,1,2,2,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm7[0,0,1,3]
@@ -271,8 +271,9 @@ define void @store_i8_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: por %xmm4, %xmm7
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,0,0,255,255,255,255,255,255,255,255,255,255,255]
; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSE-NEXT: psrldq {{.*#+}} xmm1 = xmm1[11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; SSE-NEXT: pshufhw {{.*#+}} xmm1 = xmm2[0,1,2,3,7,7,7,7]
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,2,2]
; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [255,255,0,255,255,255,255,0,255,255,255,255,255,255,255,255]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
index b7c514efff32..844dc4124016 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
@@ -288,35 +288,34 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-LABEL: store_i8_stride7_vf8:
; SSE: # %bb.0:
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movq {{.*#+}} xmm4 = mem[0],zero
; SSE-NEXT: movq {{.*#+}} xmm10 = mem[0],zero
-; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
-; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movq {{.*#+}} xmm5 = mem[0],zero
+; SSE-NEXT: movdqa %xmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
+; SSE-NEXT: movq {{.*#+}} xmm7 = mem[0],zero
+; SSE-NEXT: movdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movq {{.*#+}} xmm6 = mem[0],zero
-; SSE-NEXT: movq {{.*#+}} xmm4 = mem[0],zero
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm6[0]
-; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm1[0,0,0,0,4,5,6,7]
+; SSE-NEXT: movq {{.*#+}} xmm5 = mem[0],zero
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm3[0,0,0,0,4,5,6,7]
+; SSE-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,0,0,0]
; SSE-NEXT: movdqa {{.*#+}} xmm11 = [255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255]
; SSE-NEXT: pand %xmm11, %xmm6
-; SSE-NEXT: movdqa %xmm5, %xmm7
-; SSE-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3],xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7]
+; SSE-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: pshuflw {{.*#+}} xmm8 = xmm7[0,0,2,1,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm8[0,1,1,3]
; SSE-NEXT: pandn %xmm8, %xmm11
; SSE-NEXT: por %xmm6, %xmm11
; SSE-NEXT: movdqa {{.*#+}} xmm9 = [255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255]
-; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm0[0,0,2,1,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm4[0,0,2,1,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,0,2,1]
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0]
; SSE-NEXT: pand %xmm8, %xmm6
-; SSE-NEXT: movdqa %xmm10, %xmm3
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm10[0],xmm3[1],xmm10[1],xmm3[2],xmm10[2],xmm3[3],xmm10[3],xmm3[4],xmm10[4],xmm3[5],xmm10[5],xmm3[6],xmm10[6],xmm3[7],xmm10[7]
-; SSE-NEXT: pshuflw {{.*#+}} xmm12 = xmm3[0,2,1,3,4,5,6,7]
+; SSE-NEXT: punpcklbw {{.*#+}} xmm10 = xmm10[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm12 = xmm10[0,2,1,3,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm12 = xmm12[0,1,1,0]
; SSE-NEXT: movdqa %xmm8, %xmm13
; SSE-NEXT: pandn %xmm12, %xmm13
@@ -325,9 +324,8 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: pandn %xmm11, %xmm9
; SSE-NEXT: por %xmm13, %xmm9
; SSE-NEXT: pxor %xmm6, %xmm6
-; SSE-NEXT: movdqa %xmm4, %xmm15
-; SSE-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm4, %xmm12
+; SSE-NEXT: movdqa %xmm5, %xmm12
+; SSE-NEXT: movdqa %xmm5, %xmm15
; SSE-NEXT: punpckhbw {{.*#+}} xmm15 = xmm15[8],xmm6[8],xmm15[9],xmm6[9],xmm15[10],xmm6[10],xmm15[11],xmm6[11],xmm15[12],xmm6[12],xmm15[13],xmm6[13],xmm15[14],xmm6[14],xmm15[15],xmm6[15]
; SSE-NEXT: punpcklbw {{.*#+}} xmm12 = xmm12[0],xmm6[0],xmm12[1],xmm6[1],xmm12[2],xmm6[2],xmm12[3],xmm6[3],xmm12[4],xmm6[4],xmm12[5],xmm6[5],xmm12[6],xmm6[6],xmm12[7],xmm6[7]
; SSE-NEXT: movdqa %xmm12, %xmm13
@@ -351,20 +349,18 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[2,2,3,3]
; SSE-NEXT: movdqa %xmm1, %xmm11
; SSE-NEXT: pandn %xmm9, %xmm11
-; SSE-NEXT: pshuflw $246, {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Folded Reload
-; SSE-NEXT: # xmm9 = mem[2,1,3,3,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm9 = xmm3[2,1,3,3,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm14 = xmm9[0,0,2,1]
; SSE-NEXT: pand %xmm1, %xmm14
; SSE-NEXT: por %xmm11, %xmm14
; SSE-NEXT: movdqa {{.*#+}} xmm9 = [255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255]
; SSE-NEXT: movdqa %xmm9, %xmm11
; SSE-NEXT: pandn %xmm14, %xmm11
-; SSE-NEXT: pshufhw {{.*#+}} xmm14 = xmm3[0,1,2,3,5,6,6,7]
+; SSE-NEXT: pshufhw {{.*#+}} xmm14 = xmm10[0,1,2,3,5,6,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm14[2,2,2,2]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255]
; SSE-NEXT: movdqa %xmm0, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm14
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm4[0,2,2,3,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,1,3]
; SSE-NEXT: pand %xmm0, %xmm2
@@ -399,19 +395,19 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm11[0,0,0,0]
; SSE-NEXT: pandn %xmm11, %xmm0
; SSE-NEXT: por %xmm2, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,1,2,2]
-; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm4[1,1,2,3,4,5,6,7]
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,2,1]
-; SSE-NEXT: pand %xmm1, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm10[0,1,2,2]
+; SSE-NEXT: pshuflw {{.*#+}} xmm10 = xmm4[1,1,2,3,4,5,6,7]
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm10[0,0,2,1]
+; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm3, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
-; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm11[1,1,2,2,4,5,6,7]
+; SSE-NEXT: por %xmm10, %xmm1
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
+; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm3[1,1,2,2,4,5,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,2,1]
; SSE-NEXT: pand %xmm8, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[1,1,2,1]
-; SSE-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,5,6,4]
-; SSE-NEXT: pandn %xmm3, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm7[1,1,2,1]
+; SSE-NEXT: pshufhw {{.*#+}} xmm7 = xmm7[0,1,2,3,7,5,6,4]
+; SSE-NEXT: pandn %xmm7, %xmm8
; SSE-NEXT: por %xmm2, %xmm8
; SSE-NEXT: pand %xmm9, %xmm8
; SSE-NEXT: pandn %xmm1, %xmm9
@@ -420,27 +416,31 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; SSE-NEXT: pand %xmm1, %xmm9
; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm1, %xmm9
-; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm11[0],xmm5[1],xmm11[1],xmm5[2],xmm11[2],xmm5[3],xmm11[3],xmm5[4],xmm11[4],xmm5[5],xmm11[5],xmm5[6],xmm11[6],xmm5[7],xmm11[7]
-; SSE-NEXT: psrldq {{.*#+}} xmm5 = xmm5[11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,0,0,255,255,255,255,255,255,255,255,255,255,255]
-; SSE-NEXT: pandn %xmm5, %xmm0
-; SSE-NEXT: punpcklbw {{.*#+}} xmm10 = xmm10[0],xmm4[0],xmm10[1],xmm4[1],xmm10[2],xmm4[2],xmm10[3],xmm4[3],xmm10[4],xmm4[4],xmm10[5],xmm4[5],xmm10[6],xmm4[6],xmm10[7],xmm4[7]
-; SSE-NEXT: pshufd $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
-; SSE-NEXT: # xmm1 = mem[3,1,2,3]
-; SSE-NEXT: psrldq {{.*#+}} xmm10 = xmm10[13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; SSE-NEXT: por %xmm0, %xmm10
-; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm13[3,3,3,3,4,5,6,7]
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,0,0,255,255,255,255,255,255,255,255,255]
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,3,2,3,4,5,6,7]
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,1,4,5,6,7]
-; SSE-NEXT: pandn %xmm1, %xmm2
-; SSE-NEXT: por %xmm0, %xmm2
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
+; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,7,7,7]
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
+; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,0,0,255,255,255,255,255,255,255,255,255,255,255]
+; SSE-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,7,7,7]
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,2,2,2]
+; SSE-NEXT: pand %xmm1, %xmm2
+; SSE-NEXT: pandn %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[3,1,2,3]
+; SSE-NEXT: por %xmm2, %xmm1
+; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm13[3,3,3,3,4,5,6,7]
+; SSE-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,0,0,255,255,255,255,255,255,255,255,255]
+; SSE-NEXT: pand %xmm3, %xmm2
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,3,1,4,5,6,7]
+; SSE-NEXT: pandn %xmm0, %xmm3
+; SSE-NEXT: por %xmm2, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,0,0,0,255,255,255,255,255,255,255,255]
-; SSE-NEXT: pand %xmm0, %xmm10
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: por %xmm10, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm1
+; SSE-NEXT: pandn %xmm3, %xmm0
+; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movq %xmm0, 48(%rax)
; SSE-NEXT: movdqa %xmm9, 16(%rax)
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