[PATCH] D149095: [llvm-objdump] Support CHPE code ranges in disassembler.

[Jacek Caban via Phabricator via llvm-commits]

jacek created this revision.
jacek added reviewers: jhenderson, MaskRay.
Herald added a subscriber: zzheng.
Herald added a project: All.
jacek requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149095

Files:
  lld/test/COFF/arm64ec.test
  llvm/tools/llvm-objdump/llvm-objdump.cpp


Index: llvm/tools/llvm-objdump/llvm-objdump.cpp
===================================================================
--- llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1399,8 +1399,24 @@
                   SourcePrinter &SP, bool InlineRelocs) {
   DisassemblerTarget *DT = &PrimaryTarget;
   bool PrimaryIsThumb = false;
-  if (isArmElf(Obj))
-    PrimaryIsThumb = PrimaryTarget.SubtargetInfo->checkFeatures("+thumb-mode");
+  const chpe_range_entry *CodeMap;
+  uint32_t CodeMapCount = 0;
+
+  if (SecondaryTarget) {
+    if (isArmElf(Obj)) {
+      PrimaryIsThumb =
+          PrimaryTarget.SubtargetInfo->checkFeatures("+thumb-mode");
+    } else if (const COFFObjectFile *COFFObj = dyn_cast<COFFObjectFile>(&Obj)) {
+      const chpe_metadata *CHPEMetadata = COFFObj->getCHPEMetadata();
+      if (CHPEMetadata && CHPEMetadata->CodeMapCount) {
+        uintptr_t CodeMapInt;
+        if (Error E = COFFObj->getRvaPtr(CHPEMetadata->CodeMap, CodeMapInt))
+          reportError(std::move(E), Obj.getFileName());
+        CodeMap = reinterpret_cast<const chpe_range_entry *>(CodeMapInt);
+        CodeMapCount = CHPEMetadata->CodeMapCount;
+      }
+    }
+  }
 
   std::map<SectionRef, std::vector<RelocationRef>> RelocMap;
   if (InlineRelocs)
@@ -1575,6 +1591,24 @@
           MappingSymbols.emplace_back(Address - SectionAddr,
                                       PrimaryIsThumb ? 'p' : 's');
       }
+    } else if (CodeMapCount) {
+      DT = &PrimaryTarget;
+      for (uint32_t i = 0; i < CodeMapCount; i++) {
+        if ((CodeMap[i].StartOffset & 3) != CHPE_RANGE_AMD64)
+          continue;
+
+        // Mark x86_64 CHPE code ranges.
+        uint64_t Start = (CodeMap[i].StartOffset & ~3) +
+                         cast<COFFObjectFile>(&Obj)->getImageBase();
+        uint64_t End =
+            std::min(Start + CodeMap[i].Length, SectionAddr + SectSize);
+        if (Start < SectionAddr)
+          Start = SectionAddr;
+        if (Start < End) {
+          MappingSymbols.emplace_back(Start - SectionAddr, 's');
+          MappingSymbols.emplace_back(End - SectionAddr, 'p');
+        }
+      }
     }
 
     llvm::sort(MappingSymbols);
@@ -2156,6 +2190,21 @@
         Features.AddFeature("+thumb-mode");
       SecondaryTarget.emplace(PrimaryTarget, Features);
     }
+  } else if (const COFFObjectFile *COFFObj = dyn_cast<COFFObjectFile>(Obj)) {
+    const chpe_metadata *CHPEMetadata = COFFObj->getCHPEMetadata();
+    if (CHPEMetadata && CHPEMetadata->CodeMapCount) {
+      // Setup x86_64 disassembler for ARM64EC binaries.
+      Triple X64Triple("x86_64-windows-msvc");
+      std::string Error;
+      const Target *X64Target =
+          TargetRegistry::lookupTarget("", X64Triple, Error);
+      if (!X64Target)
+        reportError(Obj->getFileName(), "can't find X86_64 target: " + Error);
+
+      SubtargetFeatures X64Features;
+      SecondaryTarget.emplace(X64Target, *Obj, "x86_64-windows-msvc", "",
+                              X64Features);
+    }
   }
 
   const ObjectFile *DbgObj = Obj;
Index: lld/test/COFF/arm64ec.test
===================================================================
--- lld/test/COFF/arm64ec.test
+++ lld/test/COFF/arm64ec.test
@@ -37,9 +37,13 @@
 DISAS:      180001000: 52800040     mov     w0, #0x2
 DISAS-NEXT: 180001004: d65f03c0     ret
 DISAS-NEXT: ...
+DISAS-NEXT: 180002000: b8 03 00 00 00     movl    $0x3, %eax
+DISAS-NEXT: 180002005: c3                 retq
 DISAS:      180005000: 528000a0     mov     w0, #0x5
 DISAS-NEXT: 180005004: d65f03c0     ret
 DISAS-NEXT: ...
+DISAS-NEXT: 180006000: b8 06 00 00 00     movl    $0x6, %eax
+DISAS-NEXT: 180006005: c3                 retq
 
 
 #--- arm64ec-data-sym.s


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