[PATCH] D148096: [AMDGPU][GlobalISel] Widen the vector operand in G_BUILD/INSERT/EXTRACT_VECTOR

[Mateja Marjanovic via Phabricator via llvm-commits]

matejam added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:1455-1457
+          const LLT Ty = Query.Types[VecTypeIdx];
+          return Ty.getSizeInBits() < 1024 &&
+                 !SIRegisterInfo::getSGPRClassForBitWidth(Ty.getSizeInBits());
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foad wrote:
> Put this in a named LegalityPredicate - or can you just use the existing isRegisterType?
I will put it in a LegalityPredicate.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:1459-1467
+        const LLT Ty = Query.Types[VecTypeIdx];
+        unsigned NumElts = Ty.getNumElements();
+        unsigned EltSize = Ty.getElementType().getSizeInBits();
+
+        // Find the nearest legal RegClass that is larger than the current type.
+        while (!SIRegisterInfo::getSGPRClassForBitWidth(NumElts * EltSize))
+          ++NumElts;
----------------
foad wrote:
> Put this in a named LegalizeMutation
Will do.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:1593
 
   BuildVector.legalIf(isRegisterType(0));
 
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foad wrote:
> We're already checking isRegisterType here. Perhaps we just need to improve isRegisterSize so that it knows about the missing vector types?
Even if I improve isRegisterType and isRegisterSize to check if the type has a RegClass representative, it still doesn't widen the vector operand like moreElements does.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148096/new/

https://reviews.llvm.org/D148096