[llvm] e5de760 - [PowerPC] Add a new test for vperm with a swapped vector operand and a constant pool

[Maryam Moghadas via llvm-commits]

Author: Maryam Moghadas
Date: 2023-04-24T15:41:23Z
New Revision: e5de760c314c180c09787a4cb5ff4a18146ec52a

URL: https://github.com/llvm/llvm-project/commit/e5de760c314c180c09787a4cb5ff4a18146ec52a
DIFF: https://github.com/llvm/llvm-project/commit/e5de760c314c180c09787a4cb5ff4a18146ec52a.diff

LOG: [PowerPC] Add a new test for vperm with a swapped vector operand and a constant pool

This patch adds a new test that includes a vperm instruction with xxswapd as its
vector operand on little-endian Power8. The test demonstrates the constant pool
for the mask operand, which is intended to indicate the optimization of vperm
and the modification of the constant pool in subsequent patches.

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D148942

Added: 
    llvm/test/CodeGen/PowerPC/vperm-swap.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/vperm-swap.ll b/llvm/test/CodeGen/PowerPC/vperm-swap.ll
new file mode 100644
index 000000000000..6a2750faa61a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vperm-swap.ll
@@ -0,0 +1,39 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-LE-P8
+
+define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) {
+; CHECK-LE-P8: .LCPI0_0:
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   30                              # 0x1e
+; CHECK-LE-P8-NEXT: .byte   7                               # 0x7
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-NEXT: .byte   31                              # 0x1f
+; CHECK-LE-P8-LABEL: test_none_v16i8:
+; CHECK-LE-P8:       # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI0_0 at toc@ha
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
+; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI0_0 at toc@l
+; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
+; CHECK-LE-P8-NEXT:    xxswapd v3, vs1
+; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
+; CHECK-LE-P8-NEXT:    blr
+entry:
+  %lhs = load <16 x i8>, ptr %b, align 4
+  %rhs = insertelement <16 x i8> undef, i8 %arg, i32 0
+  %shuffle = shufflevector <16 x i8> %lhs, <16 x i8> %rhs, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i8> %shuffle
+}