[PATCH] D148874: [RISCV][CodeGen] Support Zfinx codegen

[Shao-Ce SUN via Phabricator via llvm-commits]

sunshaoce added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4214
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
       return FPConv;
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craig.topper wrote:
> Is FMV_W_X_RV64 correct for Zfinx?
We added this mapping in `RISCVInstrInfoF.td`: `def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;`


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8888
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
----------------
craig.topper wrote:
> Is FMV_X_ANYEXTW_RV64 correct for Zfinx?
We added this mapping in `RISCVInstrInfoF.td`: `def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;`


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  https://reviews.llvm.org/D148874/new/

https://reviews.llvm.org/D148874